Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: Techniques for reassembling scattered logic blocks in an integrated circuit (IC) are provided. The techniques include identifying a virtual memory block to be reassembled in an IC design. The virtual memory block is formed by a plurality of memory blocks that are connected by a plurality of logic circuitry. The plurality of memory blocks and the plurality logic circuitry that connect the memory blocks within the virtual memory block are identified. The identified logic circuitry and memory blocks are removed from the virtual memory block. The virtual memory block is replaced with a custom memory block that is functionally comparable to the plurality of connected memory blocks in the virtual memory block.

Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

Abstract: Techniques for reassembling scattered logic blocks in an integrated circuit (IC) are provided. The techniques include identifying a virtual memory block to be reassembled in an IC design. The virtual memory block is formed by a plurality of memory blocks that are connected by a plurality of logic circuitry. The plurality of memory blocks and the plurality logic circuitry that connect the memory blocks within the virtual memory block are identified. The identified logic circuitry and memory blocks are removed from the virtual memory block. The virtual memory block is replaced with a custom memory block that is functionally comparable to the plurality of connected memory blocks in the virtual memory block.

Abstract: Methods, computer programs and systems for using two software programs to generate a compiled design for an integrated circuit (IC) are provided. The method compiles a first IC design using a first design program and then migrates the first IC design to a second IC design, still using the first design program. Additionally, the method performs synthesis and analysis on the second IC design, still using the first design program. A second design program is used to import compile information associated with the compiling of the first IC design and the synthesis and analysis of the second IC design. The second design program is also used to create a compiled design for the second IC based on the imported compile information.

Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: Gated clock signals in ASIC designs are automatically optimized for implementation with a programmable device. Components having gated clock signals are identified and converted to operate directly from the base clock signal. To maintain compatibility, the data signal to the component is modified to connect with additional input logic responsive to a clock enable signal. The input logic modifies the signal received by the component's data input so that the component's output in response to the clock enable signal is unchanged. To this end, a system and method may identify the logic cone associated with a gated clock signal, convert this logic cone into a Boolean expression, and determine cofactors of the base clock signal from this Boolean expression. The input logic and clock enable logic are derived from an analysis of the cofactors of the base clock signal.

Abstract: Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e.g., a programmed FPGA LUT) is verified for such functional equivalence by using the specification (logical or physical) for the structured ASIC circuitry as a starting point for an FPGA design project. If the design project results in the same FPGA circuitry as it was intended that the structured ASIC circuitry would be functionally equivalent to, the structured ASIC circuitry has been verified and can be added to one or more libraries of structured ASIC modules that are available for use in providing structured ASIC products that are functionally equivalent to programmed FPGA products.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori evaluation of their design or by analyzing the results of previous compilations of their design or similar designs. An application may extract and analyze performance information from previous compilations of the design or similar designs to automatically specify the performance-critical portions of the design. The compilation software uses this specification to focus the appropriate types and amount of optimization on different portions of the design. The compilation software may use additional optimization techniques and/or may allocate additional computing resources to optimize the performance of performance-critical portions of the design. Other portions of the design that are not performance-critical may be optimized using balanced optimization techniques.