Abstract: A programmable logic device architecture providing efficient configurable functionality to allow the “tie-off” of logic region-wide control signals. This functionality is provided while maintaining the efficiency of region-wide signals, yet allows sufficient flexibility for effective use of register-packing and usage within the region. Methods are given for both sub-region and individual logic element tie-off granularity. In various embodiments, the tie-off logic may be used for logic wide signals used in PLDs having logic elements arranged in regions of logic, sometimes referred to in the industry as either Logic Array Blocks or Complex Logic Blocks.