Patents by Inventor Jinyu FU

Jinyu FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure and fabrication method thereof
    Patent number: 11515400
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: November 29, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Ruizhi Tang, Jinyu Fu, Lin Liu, Bo Li, Peng Yang, Haojun Huang, Jialei Liu
  • SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20210074829
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 11, 2021
    Inventors: Ruizhi TANG, Jinyu FU, Lin LIU, Bo LI, Peng YANG, Haojun HUANG, Jialei LIU