Patents by Inventor Jinzheng Miao

Jinzheng Miao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10686070
    Abstract: A trench-gate MOSFET is disclosed. A plurality of trenches penetrating through a well region are formed in a semiconductor substrate, and horizontal widths of the trenches are defined by first openings formed. The trenches are filled with polysilicon gates. The first openings at the tops of the polysilicon gates are filled with a first dielectric layer. Under the self-alignment definition of the first dielectric layer, the portions, between the first openings, of the hard mask layer are removed to form second openings. First inner spacers are formed through self-alignment on inner sides of the second openings, and the second openings are narrowed by the first inner spacers to form third openings. The third openings are filled with a metal layer, so that a source contact hole is formed through self-alignment at the top of the source region. A method for manufacturing a trench-gate MOSFET is further disclosed.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 16, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Lei Shi, Jinzheng Miao, Rangxuan Fan
  • Publication number: 20200075763
    Abstract: A trench-gate MOSFET is disclosed. A plurality of trenches penetrating through a well region are formed in a semiconductor substrate, and horizontal widths of the trenches are defined by first openings formed. The trenches are filled with polysilicon gates. The first openings at the tops of the polysilicon gates are filled with a first dielectric layer. Under the self-alignment definition of the first dielectric layer, the portions, between the first openings, of the hard mask layer are removed to form second openings. First inner spacers are formed through self-alignment on inner sides of the second openings, and the second openings are narrowed by the first inner spacers to form third openings. The third openings are filled with a metal layer, so that a source contact hole is formed through self-alignment at the top of the source region. A method for manufacturing a trench-gate MOSFET is further disclosed.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 5, 2020
    Applicant: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Lei SHI, Jinzheng MIAO, Rangxuan FAN
  • Patent number: 9761695
    Abstract: A method for fabricating a shield gate trench MOSFET, including the following steps: forming a hard mask layer and defining a gate forming region; forming a top trench by means of both anisotropic and isotropic etching; forming an oxidative barrier layer; etching back the oxidative barrier layer, and then forming a bottom trench by means of anisotropic etching; forming a bottom oxidative layer by means of thermal oxidative self-alignment; removing the oxidative barrier layer; forming a gate dielectric film; forming a first polysilicon layer; etching back the first polysilicon layer to form respectively therefrom a polysilicon gate and a bottom shield polysilicon; forming a inter-poly dielectric isolation layer; etching back the inter-poly dielectric isolation layer; forming a second polysilicon layer and forming a shield polysilicon by means of superposition with the bottom shield polysilicon.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 12, 2017
    Assignee: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
    Inventors: Rangxuan Fan, Jinzheng Miao