Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.

Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.

Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.

Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.

Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.

Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.

Abstract: A method for simulating multiple processors in parallel is provided. The scheduler create one or more slave threads using a master thread, and determines a processor that is simulated by the master thread and a processor that is simulated by a slave thread, so that the scheduler is capable of using the master thread and the one or more slave threads to invoke, through a first execute interface, the determined processor that is simulated by the master thread and the determined processor that is simulated by the slave thread to execute a corresponding instruction, where the first execute interface is registered with the scheduler by the determined processor that is simulated by the master thread and the determined processor that is simulated by the slave thread. Thus simulation efficiency can be increased and resource utilization can be improved.