Abstract: A gate structure of split-gate MOSFET includes a substrate, an epitaxial layer, a first gate, a second gate, a bottom dielectric layer between the first gate and the epitaxial layer, a gate dielectric layer between the second gate and the epitaxial layer, and an inter-gate dielectric layer between the first and second gates. The epitaxial layer is on the substrate having first and second trenches with different extending directions, wherein the first trench and the second trench have an overlapping region. The width of the first trench is greater than that of the second trench. The depth of the first trench is greater than that of the second trench. The first gate is in the first trench. The second gate is in the first trench on the first gate and in the second trenches.

Abstract: A split-gate MOSFET includes first and second epitaxial layers, first, second, and third gates, a gate oxide layer, a trench oxide layer, and a trench implantation region formed on a substrate in order. The second epitaxial layer has a doping concentration greater than that of the first epitaxial layer. A plurality of trenches is in the first and second epitaxial layers. Both the first and second gates are located in each of the trenches in a cell region. The third gates are located in each of the trenches in a terminal region. The third gate closest to the cell region is grounded, and the others are floating. The gate oxide layer is disposed between the first and second gates. The trench oxide layer is located between the first gate and the first epitaxial layer and located between the trench surface and the third gate. The trench implantation region is located in the first epitaxial layer at the bottom of the trench and has a doping concentration less than that of the first epitaxial layer.

Abstract: An adaptive duo-gate MOSFET includes a trench MOSFET and an adaptive element. The trench MOSFET includes a source, a drain, a first gate, a second gate, and a dielectric layer between the first and second gates. Herein, the first gate may generate charge-coupling in blocking operation, and the second gate may form channel in the trench MOSFET when in conduction operation. The adaptive element is electrically coupled to the first gate, the second gate, and the source respectively. When a potential difference between the second gate and the source is larger than a predetermined value, the first gate and the source are electrically disconnected and then the first gate and the second gate are electrically connected. After a predetermined time, the first gate and the second gate are electrically disconnected and then the first gate and the source are electrically connected.

Abstract: An adaptive duo-gate MOSFET includes a trench MOSFET and an adaptive element. The trench MOSFET includes a source, a drain, a first gate, a second gate, and a dielectric layer between the first and second gates. Herein, the first gate may generate charge-coupling in blocking operation, and the second gate may form channel in the trench MOSFET when in conduction operation. The adaptive element is electrically coupled to the first gate, the second gate, and the source respectively. When a potential difference between the second gate and the source is larger than a predetermined value, the first gate and the source are electrically disconnected and then the first gate and the second gate are electrically connected. After a predetermined time, the first gate and the second gate are electrically disconnected and then the first gate and the source are electrically connected.

Abstract: A mixer for down-converting an input signal to an output signal is disclosed. The mixer includes an amplifying circuit and a down-converting circuit. The amplifying circuit is utilized for amplifying the input signal to generate an amplified signal. The down-converting circuit includes a filtering module, a loading module, and a down-converting module. The filtering module is coupled to the amplifying circuit, and is utilized for filtering low-frequency components in the amplified signal. The loading module is coupled to the amplifying circuit and a predetermined voltage level, and is utilized for providing a DC bias voltage to the amplifying circuit. The down-converting module is coupled to the filtering module and the predetermined voltage level, and is utilized for generating the output signal according to a local oscillating signal.

Abstract: A piezoelectric actuator system with a position detection function includes an immovable base, a piezoelectric material, a drive shaft, and a movable part. The immovable base has a driving circuit for providing a driving voltage. The piezoelectric material is fixed on the immovable base and electrically coupled to the driving circuit. A length of the piezoelectric material is controlled by the driving voltage. The drive shaft is fixed on the piezoelectric material and has at least two conductive parts having impedance materials. The movable part is disposed on the drive shaft, and a spacer made of a conductive material is installed at its bottom. The two conductive parts are electrically coupled to the spacer, so as to form a conduction path. The driving circuit detects an impedance of the conduction path to determine a position of the movable part.

Abstract: A mixer for down-converting an input signal to an output signal is disclosed. The mixer includes an amplifying circuit and a down-converting circuit. The amplifying circuit is utilized for amplifying the input signal to generate an amplified signal. The down-converting circuit includes a filtering module, a loading module, and a down-converting module. The filtering module is coupled to the amplifying circuit, and is utilized for filtering low-frequency components in the amplified signal. The loading module is coupled to the amplifying circuit and a predetermined voltage level, and is utilized for providing a DC bias voltage to the amplifying circuit. The down-converting module is coupled to the filtering module and the predetermined voltage level, and is utilized for generating the output signal according to a local oscillating signal.

Abstract: A low noise amplifier has the properties of low noise figure and high gain under a high-frequency operation. The low noise amplifier includes a first transistor, a first inductive impedance, a first gate voltage source, a matching circuit, an input, a second inductive impedance, a second transistor, a first capacitive impedance, a second gate voltage source, a third transistor, a third gate voltage source, a second capacitive impedance, a first impedance, a second impedance, a direct current source, a first output, a second output, a first resistor, a second resistor, a third resistor, a first bulk voltage source, a second bulk voltage source, and a third bulk voltage source.

Abstract: A low noise amplifier has the properties of low noise figure and high gain under a high-frequency operation. The low noise amplifier includes a first transistor, a first inductive impedance, a first gate voltage source, a matching circuit, an input, a second inductive impedance, a second transistor, a first capacitive impedance, a second gate voltage source, a third transistor, a third gate voltage source, a second capacitive impedance, a first impedance, a second impedance, a direct current source, a first output, a second output, a first resistor, a second resistor, a third resistor, a first bulk voltage source, a second bulk voltage source, and a third bulk voltage source.

Abstract: high-gain and low-noise low noise amplifier (LNA) includes a differential amplifier, a pre-amplifier and an impedance matching network. The differential amplifier includes a first input end and a second input end coupled to a grounded impedance. The pre-amplifier includes an input end and an output end. The impedance matching network is coupled between the first input end of the differential amplifier and the output end of the pre-amplifier for matching an input impedance of the differential amplifier with an output impedance of the pre-amplifier. The present invention provides a LNA structure with low noise, high gain and easy design.

Abstract: A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.

Abstract: A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.

Abstract: A high-gain and low-noise low noise amplifier (LNA) includes a differential amplifier, a pre-amplifier and an impedance matching network. The differential amplifier includes a first input end and a second input end coupled to a grounded impedance. The pre-amplifier includes an input end and an output end. The impedance matching network is coupled between the first input end of the differential amplifier and the output end of the pre-amplifier for matching an input impedance of the differential amplifier with an output impedance of the pre-amplifier. The present invention provides a LNA structure with low noise, high gain and easy design.

Abstract: A semiconductor device having an inductor including a planar coil portion forming an opening in the center thereof and a core received in the opening and extending above and below the planar coil portion. A first and a second inter-metal dielectric layer, and the inductor further including a first connecting leg including an electrically conductive material. The first connecting leg is connected to the planar coil portion. The planar coil portion is in the first inter-metal dielectric layer and the first connecting leg is in the second inter-metal dielectric layer. The inductor further includes a second connecting leg connected to the planar coil portion, and an electrically conductive bump connected to the second connecting leg.

Abstract: Within both a method for fabricating a microelectronic inductor structure, and the microelectronic inductor structure fabricated employing the method, there is formed over a substrate a spirally patterned conductor layer. Within both the method and the microelectronic inductor structure there is also formed over the substrate and annularly surrounding the spirally patterned conductor layer an annular magnetic shielding layer.