Abstract: A double-stepping linkage pedal for a bass drum of a jazz drum is provided, in which a left pedal assembly is connected to a left hammerhead assembly, so that a front end of the left pedal assembly moves up and down to drive the left hammerhead assembly to swing back and forth. A left tension spring assembly and the left hammerhead assembly are elastically linked to the left pedal assembly in a swinging direction front-rear consistent manner. A right pedal assembly is drivingly connected to a right hammerhead assembly in a front-rear swinging manner, so that a front end of the right pedal assembly moves up and down to drive the right hammerhead assembly to swing back and forth. A right tension spring assembly and the right hammerhead assembly are elastically linked to the right pedal assembly in a swinging direction front-rear consistent manner.

Abstract: A double-stepping linkage pedal for a bass drum of a jazz drum is provided, in which a left pedal assembly is connected to a left hammerhead assembly, so that a front end of the left pedal assembly moves up and down to drive the left hammerhead assembly to swing back and forth. A left tension spring assembly and the left hammerhead assembly are elastically linked to the left pedal assembly in a swinging direction front-rear consistent manner. A right pedal assembly is drivingly connected to a right hammerhead assembly in a front-rear swinging manner, so that a front end of the right pedal assembly moves up and down to drive the right hammerhead assembly to swing back and forth. A right tension spring assembly and the right hammerhead assembly are elastically linked to the right pedal assembly in a swinging direction front-rear consistent manner.

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

Abstract: A two-dimensional three-degree-of-freedom micro-motion platform structure for high-precision positioning and measurement. Two series flexible hinges are connected in parallel to form a moving pair. One end of the moving pair is fixed, and driving force is applied to the other end. The driving force is amplified by means of a lever to drive the moving pair to translate and rotate. The moving pair drives a first flexible hinge of a platform to rotate, thereby driving the platform to produce corresponding displacement. Four identical moving pairs and four identical first flexible hinges respectively constitute four branch hinges which are different in arrangement; two branch hinges opposite to the platform are in central symmetry and constitute one group, and the four branch hinges are divided into two groups in total.

Abstract: A two-dimensional three-degree-of-freedom micro-motion platform structure for high-precision positioning and measurement. Two series flexible hinges are connected in parallel to form a moving pair. One end of the moving pair is fixed, and driving force is applied to the other end. The driving force is amplified by means of a lever to drive the moving pair to translate and rotate. The moving pair drives a first flexible hinge of a platform to rotate, thereby driving the platform to produce corresponding displacement. Four identical moving pairs and four identical first flexible hinges respectively constitute four branch hinges which are different in arrangement; two branch hinges opposite to the platform are in central symmetry and constitute one group, and the four branch hinges are divided into two groups in total.

Abstract: Disclosed is a method for evaluating a health status of mechanical equipment. Firstly, status data of main components on mechanical equipment are collected by a sensor, and feature extraction is performed to obtain feature parameters. Then, noise data and fault data are extracted by an outlier detection algorithm, and only the fault data are retained. Subsequently, dimension reduction processing is performed to obtain a feature vector for final evaluation. Finally, equipment status evaluation is performed, a self-organizing map neural network model is established by health status data and failure status data, rate impact factors of each group of data to be evaluated are calculated by an entropy weight theory, and the rate impact factors are introduced into a neural network to perform health factor calculation. The present invention implements overall status evaluation for mechanical equipment, provides a basis for health maintenance of the mechanical equipment, and avoids unnecessary economic losses.

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

Abstract: The invention relates to a magnetic suspension technology field, especially to a self-luminous suspension lamp, comprising a wireless charging device, a floater in which a light-emitting device and a magnet being configured, an electromagnetic coil configured below the floater, a suspension control system connected to the electromagnetic coil. The magnetic force generated by the electromagnetic coil keeps balance to the gravity of the whole floater so that the floater is suspended. A Hall sensor is configured below the floater, the displacement of the floater will cause the feedback of the Hall sensor. The suspension controller varies the output power according to the result of the feedback of the Hall sensor, to keep the floater in a stable status in real time. Hence, the invention provides a beauty and an effect of science for the domestic illumination, and provides an enjoyment for the life.

Abstract: A semiconductor structure may implement a metal-oxide-metal capacitor. When layer design rules change from one layer to the next, the structure may change the direction of the interleaved plates of the capacitor. For example, when the metallization width or spacing design rules change from layer M3 to layer M4, the structure may run the capacitor traces in different directions (e.g., orthogonal to one another) on M3 as compared to M4. Among the layers that adhere to the same design rules, for example layers M1, M2, and M3, the structure may run the capacitor traces in the same direction in each of the layers M1, M2, and M3. In this way, the capacitor traces overlap to large extent without misalignment on layers that have the same design rules, and the structure avoids misalignment of the capacitor traces when the design rules change.

Abstract: A semiconductor structure may implement a metal-oxide-metal capacitor. When layer design rules change from one layer to the next, the structure may change the direction of the interleaved plates of the capacitor. For example, when the metallization width or spacing design rules change from layer M3 to layer M4, the structure may run the capacitor traces in different directions (e.g., orthogonal to one another) on M3 as compared to M4. Among the layers that adhere to the same design rules, for example layers M1, M2, and M3, the structure may run the capacitor traces in the same direction in each of the layers M1, M2, and M3. In this way, the capacitor traces overlap to large extent without misalignment on layers that have the same design rules, and the structure avoids misalignment of the capacitor traces when the design rules change.

Abstract: According to an exemplary embodiment, a power clamp for providing on-chip ESD and mistrigger event protection includes a clamping transistor coupled between a power bus and a ground. The power clamp further includes a number of inverter stages coupled in series, where a first inverter stage has an output coupled to the clamping transistor. The power clamp further includes a turn-off resistor coupled between the power bus and an input of the first inverter. The turn-off resistor is configured to cause the clamping transistor to automatically turn off after having been turned on. The turn-off resistor determines a period of time that the clamping transistor is turned on after an ESD or mistrigger event has occurred on the power bus. The power clamp further includes a timing circuit coupled to the inverter stages. The power clamp further includes a feedback transistor coupled between a second inverter stage and the power bus.

Abstract: According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situated between the first and second active regions. The ESD protection structure further includes at least one contact-via chain connected to the first active region, where the at least one contact-via chain includes a contact connected to a via. The at least one contact-via chain forms a ballast resistor for increased ESD current distribution uniformity. The contact is connected to the via by a first metal segment situated in a first interconnect metal layer of a die. The at least one contact-via chain is connected between the first active region and a second metal segment situated in a second interconnect metal layer of the die.

Abstract: According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situated between the first and second active regions. The ESD protection structure further includes at least one contact-via chain connected to the first active region, where the at least one contact-via chain includes a contact connected to a via. The at least one contact-via chain forms a ballast resistor for increased ESD current distribution uniformity. The contact is connected to the via by a first metal segment situated in a first interconnect metal layer of a die. The at least one contact-via chain is connected between the first active region and a second metal segment situated in a second interconnect metal layer of the die.

Abstract: A spiral inductor is provided including a substrate and an inductor dielectric layer over the substrate having a spiral opening provided therein. The spiral inductor is in the spiral opening with the spiral inductor including a plurality of parallel spiral vias connected together at center proximate and center distal ends of the spiral inductor.

Abstract: Genetic polymorphisms responsible or associated with altered expression of cytochrome P450 CYP3A5 enzyme are described. Single nucleotide polymorphisms are provided. Methods for identifying subjects having a low or high drug metabolizing phenotype associated with CYP3A5 expression are provided. Assays, kits and methods for determining and assaying the CYP3A5 genotype and phenotype of individual patients are disclosed. Oligonucleotide probes and primers for use in the assays, kits and methods are described. Assays and methods for determining and evaluating an individual's metabolism of drugs and therapeutic agents, the potential for drug interactions, and thereby toxicity and effectiveness of certain drugs and treatment modalities, are provided.

Abstract: Genetic polymorphisms responsible or associated with altered expression of cytochrome P450 CYP3A5 enzyme are described. Single nucleotide polymorphisms are provided. Methods for identifying subjects having a low or high drug metabolizing phenotype associated with CYP3A5 expression are provided. Assays, kits and methods for determining and assaying the CYP3A5 genotype and phenotype of individual patients are disclosed. Oligonucleotide probes and primers for use in the assays, kits and methods are described. Assays and methods for determining and evaluating an individual's metabolism of drugs and therapeutic agents, the potential for drug interactions, and thereby toxicity and effectiveness of certain drugs and treatment modalities, are provided.

Abstract: Genetic polymorphisms responsible or associated with altered expression of cytochrome P450 CYP3A5 enzyme are described. Single nucleotide polymorphisms are provided. Methods for identifying subjects having a low or high drug metabolizing phenotype associated with CYP3A5 expression are provided. Assays, kits and methods for determining and assaying the CYP3A5 genotype and phenotype of individual patients are disclosed. Oligonucleotide probes and primers for use in the assays, kits and methods are described. Assays and methods for determining and evaluating an individual's metabolism of drugs and therapeutic agents, the potential for drug interactions, and thereby toxicity and effectiveness of certain drugs and treatment modalities, are provided.

Abstract: A process of fabricating a sub-micron MOSFET device, featuring a high dielectric constant gate insulator layer, and a metal gate structure, has been developed. Processes performed at temperatures detrimental to the high dielectric, gate insulator layer, such as formation of spacers on the sides of subsequent gate structures, as well as formation of source/drain regions, are introduced prior to the formation of the high dielectric, gate insulator layer. This is accomplished via use of a dummy gate structure, comprised of silicon nitride, used as a mask to define the source/drain regions, and used as the structure in which sidewall spacers are formed on. After selective removal of the dummy gate structure, creating an opening in an interlevel dielectric layer exposing the MOSFET channel region, deposition of the high dielectric, gate insulator layer, on the surface of the MOSFET channel region, is performed.

Abstract: A process for fabricating a MOSFET device, featuring a narrow lateral delta doping, or a narrow anti-punchthrough region, located in the center of the MOSFET channel region, has been developed. The process features formation of the narrow, anti-punchthrough region, via use of an ion implantation procedure, performed using an opening, comprised with sidewall spacers, as an implant mask. After formation of the narrow, anti-punchthrough region, the sidewall spacers are removed, and a gate insulator layer, and a polysilicon gate structure, are formed in the spacerless opening, defining a channel region wider than the narrow, anti-punchthrough region.