Patents by Inventor Jiongxin Lu

Jiongxin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162134
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
  • Publication number: 20240105545
    Abstract: Semiconductor packages including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Jiongxin Lu, Kunzhong Hu, Jun Zhai, Sanjay Dabral
  • Publication number: 20240105704
    Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets. A heat spreader may be bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding. The chiplets within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 28, 2024
    Inventors: Chonghua Zhong, Jiongxin Lu, Kunzhong Hu, Jun Zhai, Sanjay Dabral
  • Publication number: 20240105702
    Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.
    Type: Application
    Filed: March 6, 2023
    Publication date: March 28, 2024
    Inventors: Chonghua Zhong, Jiongxin Lu, Kunzhong Hu, Jun Zhai, Sanjay Dabral
  • Patent number: 11916003
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Xiao Lu, Jiongxin Lu, Christopher Combs, Alexander Huettis, John Harper, Jieping Zhang, Nachiket R. Raravikar, Pramod Malatkar, Steven A. Klein, Carl Deppisch, Mohit Sood
  • Publication number: 20230017445
    Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 19, 2023
    Inventors: Kunzhong Hu, Chonghua Zhong, Jiongxin Lu, Jun Zhai
  • Patent number: 11404337
    Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 2, 2022
    Assignee: Apple Inc.
    Inventors: Kunzhong Hu, Chonghua Zhong, Jiongxin Lu, Jun Zhai
  • Publication number: 20210202332
    Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. In an embodiment, the interposer is stacked on the package substrate and joined with a conductive film. In an embodiment the interposer is formed on the package substrate during a reconstitution sequence.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Kunzhong Hu, Chonghua Zhong, Jiongxin Lu, Jun Zhai
  • Publication number: 20210082798
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
  • Publication number: 20190304805
    Abstract: An electronic package including a substrate. The substrate includes a first solder material that is applied adjacent a periphery of the substrate. The substrate also includes a second solder material having properties different than the first solder material that is applied adjacent a periphery of a keep in zone of the substrate.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Jiongxin Lu, Aravindha Antoniswamy, Jinlin Wang, Ashutosh Srivastava
  • Publication number: 20170053858
    Abstract: Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: Jan Krajniak, Carl L. Deppisch, Kabirkumar J. Mirpuri, Hongjin Jiang, Fay Hua, Yuying Wei, Beverly J. Canham, Jiongxin Lu, Mukul P. Renavikar