Abstract: Cleansing compositions can include hinokitiol; and a 2-pyridinol N-oxide material; wherein the ratio by weight of the 2-pyridinol N-oxide material to the hinokitiol is about 1:4 to about 2:1 and the combination of the 2-pyridinol N-oxide material and hinokitiol includes about 9 ppm or more by weight of the cleansing composition.

Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.

Abstract: Cleansing compositions can include hinokitiol; and a 2-pyridinol N-oxide material; wherein the ratio by weight of the 2-pyridinol N-oxide material to the hinokitiol is about 1:4 to about 2:1 and the combination of the 2-pyridinol N-oxide material and hinokitiol includes about 9 ppm or more by weight of the cleansing composition.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a bottom substrate having a first region and a second region; an insulation layer formed on the bottom substrate in the first region; a top substrate on side surface of the trench and the insulation layer; a first fin portion formed over the insulation layer, and a gate structure crossing the first fin portion. The first fin portion is electrically isolated from the bottom substrate through the insulation layer to reduce the leakage current at the bottom of the first fin portion. The gate structure covers part of side and top surfaces of the first fin portion.

Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a bottom substrate having a first region and a second region; an insulation layer formed on the bottom substrate in the first region; a top substrate on side surface of the trench and the insulation layer; a first fin portion formed over the insulation layer, and a gate structure crossing the first fin portion. The first fin portion is electrically isolated from the bottom substrate through the insulation layer to reduce the leakage current at the bottom of the first fin portion. The gate structure covers part of side and top surfaces of the first fin portion.

Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.

Abstract: In some embodiments, a contact via and a fabricating method thereof are provided. The method can comprise: providing a substrate; forming a buffer layer in the substrate; forming a dielectric layer covering the substrate and the buffer layer; forming a through hole in the dielectric layer, wherein a bottom of the through hole exposes a surface of the buffer layer; performing a roughening treatment to the exposed surface of the buffer layer to increase a roughness of the exposed surface of the buffer layer; forming a barrier layer in the through hole, and reducing a thickness of a portion of the barrier layer at the bottom of the through hole; and filling a conductive material into the through hole to form a contact via.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the first region, wherein the insulation layer exposes part of side surface of the trench, and forming a top substrate on the exposed side surface of the trench and the insulation layer. Further, the method includes forming a first fin portion in the first region, and forming a gate structure crossing the first fin portion, wherein the gate structure covers part of side and top surfaces of the first fin portion.

Abstract: In some embodiments, a contact via and a fabricating method thereof are provided. The method can comprise: providing a substrate; forming a buffer layer in the substrate; forming a dielectric layer covering the substrate and the buffer layer; forming a through hole in the dielectric layer, wherein a bottom of the through hole exposes a surface of the buffer layer; performing a roughening treatment to the exposed surface of the buffer layer to increase a roughness of the exposed surface of the buffer layer; forming a barrier layer in the through hole, and reducing a thickness of a portion of the barrier layer at the bottom of the through hole; and filling a conductive material into the through hole to form a contact via.

Abstract: Packaging is provided for high moisture bar soap compositions to address a number of potential problems associated with high moisture bar soap compositions, such as minimizing moisture loss, inhibiting mold growth on paperboard material used in the packaging, and preventing the development of colored stains on the bar soap and packaging resulting from chemical reaction between the high moisture bar soap and the paperboard, especially recycled paperboard. The bar soap packaging comprises a laminate material comprising a paperboard material, a thermoplastic material disposed on at least one side of the paperboard material, and a fungicide.

Abstract: Packaging is provided for high moisture bar soap compositions to address a number of potential problems associated with high moisture bar soap compositions, such as minimizing moisture loss, inhibiting mold growth on paperboard material used in the packaging, and preventing the development of colored stains on the bar soap and packaging resulting from chemical reaction between the high moisture bar soap and the paperboard, especially recycled paperboard. The bar soap packaging comprises a laminate material comprising a paperboard material, a thermoplastic material disposed on at least one side of the paperboard material, and a fungicide.