Patents by Inventor Jiraphat Charoenratpratoom

Jiraphat Charoenratpratoom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240003768
    Abstract: A semiconductor device has a substrate and a first electrical component including a sensing region disposed over the substrate. The sensing region can be responsive to external stimuli, such as pressure. A cover lid is disposed over the first electrical component and extending to the substrate with an opening in the cover lid aligned over the sensing region. A gel material is disposed within the opening of the cover lid to seal the sensing region with respect to an environment condition, such as liquid. A bond wire is coupled between the first electrical component and substrate. An adhesive layer is disposed around a perimeter of the sensing area and the cover lid is bonded to the adhesive layer. A second electrical component is disposed on the substrate and the first electrical component is disposed on the second electrical component.
    Type: Application
    Filed: June 14, 2023
    Publication date: January 4, 2024
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Paweena Phatto, Maythichai Saithong, Eakkasit Dumsong, Jiraphat Charoenratpratoom
  • Patent number: 11784102
    Abstract: A semiconductor package and method for forming thereof are disclosed. The package includes a package substrate having a die cavity with a die attached therein. The package substrate also includes a cavity for bonding a cap thereto to form a hermetic package. The cap is bonded to the cavity using sealing rings.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: October 10, 2023
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Eakkasit Dumsong, Mike Jayson Candelario, Phongsak Sawasdee, Jiraphat Charoenratpratoom, Paweena Phatto, Maythichai Saithong
  • Publication number: 20220208746
    Abstract: An embodiment related to a package is disclosed. The package includes a component mounted to a die attach region on a package substrate. A passive component with first and second passive component terminals is vertically attached to the package substrate. An encapsulant is disposed over the package substrate to encapsulate the package. In one embodiment, an external component is stacked above the encapsulant and is electrically coupled to the encapsulated package.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 30, 2022
    Inventors: Jiraphat Charoenratpratoom, Phongsak Sawasdee, Wannasat Panphrom
  • Publication number: 20220037219
    Abstract: A semiconductor package and method for forming thereof are disclosed. The package includes a package substrate having a die cavity with a die attached therein. The package substrate also includes a cavity for bonding a cap thereto to form a hermetic package. The cap is bonded to the cavity using sealing rings.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 3, 2022
    Inventors: Eakkasit DUMSONG, Mike Jayson CANDELARIO, Phongsak Sawasdee, Jiraphat Charoenratpratoom, Paweena PHATTO, Maythichai SAITHONG