Patents by Inventor Jiren Yuan
Jiren Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8174423Abstract: The present invention introduces a sub-converter stage used in a pipelined analog-to-digital converter. The sub-converter stage comprises an amplifier with a gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C??C, and customized reference signal Vrefk, where ? ? ? C C = 4 A + 2 and V refk = V ref ? ( 1 - ? ? ? C 2 ? C ) . If the gain A of the amplifier is adjustable, the sub-converter stage needs an error detector to detect the difference between the output of the amplifier and reference signal Vref and adjust the gain A of the amplifier. The present invention also introduces a pipelined analog-to-digital converter employing the sub-converter stage.Type: GrantFiled: September 23, 2010Date of Patent: May 8, 2012Assignee: Emensa Technology Ltd. Co.Inventors: Cheng Chen, Jiren Yuan
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Publication number: 20110285563Abstract: The present invention introduces a sub-converter stage used in a pipelined analog-to-digital converter. The sub-converter stage comprises an amplifier with a gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C??C, and customized reference signal Vrefk, where ? ? ? C C = 4 A + 2 and V refk = V ref ? ( 1 - ? ? ? C 2 ? C ) . If the gain A of the amplifier is adjustable, the sub-converter stage needs an error detector to detect the difference between the output of the amplifier and reference signal Vref and adjust the gain A of the amplifier. The present invention also introduces a pipelined analog-to-digital converter employing the sub-converter stage.Type: ApplicationFiled: September 23, 2010Publication date: November 24, 2011Applicant: EMENSA TECHNOLOGY LTD. CO.Inventors: Cheng CHEN, Jiren YUAN
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Patent number: 8035421Abstract: A charge sampling circuit, has a control signal generator for controlling an analog input signal to the charge sampling circuit to be integrated by an integrator during a sampling phase responsive to a sampling signal from the control signal generator. The current of the analog input signal is integrated to an integrated charge for producing a proportional voltage or current sample at a signal output at the end of the sampling phase.Type: GrantFiled: April 6, 2005Date of Patent: October 11, 2011Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventor: Jiren Yuan
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Patent number: 7612703Abstract: The present invention relates to an analog-to-digital converter, especially to a pipelined analog-to-digital converter with calibration of capacitor mismatch and finite gain error. Comparing with the conventional pipelined analog-to-digital converter, the new analog-to-digital converter comprises more circuit blocks including an extra sub-converter stage, a control clock generator and an error detector, resulting in that each sub-converter stage has two operation modes: normal conversion mode and calibration mode. All of the sub-converter stages share one error detector which amplifies the output of the sub-converter stage in calibration mode. Furthermore, to store the output of the error detector, a memory is used in each sub-converter stage for controlling the gain of amplifier in order to make the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign.Type: GrantFiled: June 10, 2008Date of Patent: November 3, 2009Assignee: Emensa Technology Ltd. Co.Inventors: Cheng Chen, Jiren Yuan
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Publication number: 20090189796Abstract: The present invention relates to an analog-to-digital converter, especially to a pipelined analog-to-digital converter with calibration of capacitor mismatch and finite gain error. Comparing with the conventional pipelined analog-to-digital converter, the new analog-to-digital converter comprises more circuit blocks including an extra sub-converter stage, a control clock generator and an error detector, resulting in that each sub-converter stage has two operation modes: normal conversion mode and calibration mode. All of the sub-converter stages share one error detector which amplifies the output of the sub-converter stage in calibration mode. Furthermore, to store the output of the error detector, a memory is used in each sub-converter stage for controlling the gain of amplifier in order to make the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign.Type: ApplicationFiled: June 10, 2008Publication date: July 30, 2009Applicant: EMENSA TECHNOLOGY LTD. CO.Inventors: Cheng Chen, Jiren Yuan
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Patent number: 7164328Abstract: Various embodiments of a direct digital amplitude modulator (DDAM) for modulating radio frequency (RF) or intermediate frequency (IF) or baseband signal with the invented interpolation technique are disclosed. The interpolation technique greatly reduces the amplitudes of alias signals without using an analog filter. The embodiments therefore are significant for various communication transmitters to achieve simple structure, good linearity and high power efficiency.Type: GrantFiled: April 30, 2003Date of Patent: January 16, 2007Assignee: Infineon Technologies Wireless Solutions Sweden ABInventors: Jiren Yuan, Yijun Zhou
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Patent number: 7053673Abstract: A charge sampling circuit, having a control signal generator for controlling an analog input signal to the charge sampling circuit to be integrated by an integrator during a sampling phase responsive to a sampling signal from the control signal generator is presented. The current of the analog input signal is integrated to an integrated charge for producing one of a proportional voltage and current sample at a signal output at the end of the sampling phase.Type: GrantFiled: September 28, 2000Date of Patent: May 30, 2006Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventor: Jiren Yuan
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Patent number: 7023245Abstract: A charge sampling circuit, has a control signal generator for controlling an analog input signal to the charge sampling circuit to be integrated by an integrator during a sampling phase responsive to a sampling signal from the control signal generator. The current of the analog input signal is integrated to an integrated charge for producing a proportional voltage or current sample at a signal output at the end of the sampling phase.Type: GrantFiled: April 6, 2005Date of Patent: April 4, 2006Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventor: Jiren Yuan
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Publication number: 20050176397Abstract: A charge sampling circuit, has a control signal generator for controlling an analog input signal to the charge sampling circuit to be integrated by an integrator during a sampling phase responsive to a sampling signal from the control signal generator. The current of the analog input signal is integrated to an integrated charge for producing a proportional voltage or current sample at a signal output at the end of the sampling phase.Type: ApplicationFiled: April 6, 2005Publication date: August 11, 2005Inventor: Jiren Yuan
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Publication number: 20050168371Abstract: A charge sampling circuit, has a control signal generator for controlling an analog input signal to the charge sampling circuit to be integrated by an integrator during a sampling phase responsive to a sampling signal from the control signal generator. The current of the analog input signal is integrated to an integrated charge for producing a proportional voltage or current sample at a signal output at the end of the sampling phase.Type: ApplicationFiled: April 6, 2005Publication date: August 4, 2005Inventor: Jiren Yuan
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Publication number: 20050074073Abstract: Various embodiments of a direct digital amplitude modulator (DDAM) for modulating radio frequency (RF) or intermediate frequency (IF) or baseband signal with the invented interpolation technique are disclosed. The interpolation technique greatly reduces the amplitudes of alias signals without using an analog filter. The embodiments therefore are significant for various communication transmitters to achieve simple structure, good linearity and high power efficiency.Type: ApplicationFiled: April 30, 2003Publication date: April 7, 2005Inventors: Jiren Yuan, Yijun Zhou
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Patent number: 6317070Abstract: The demand on very high resolution A/D converter can be eliminated by using the invented floating-point A/D converter when the resolution is merely used for covering the signal dynamic range rather than the quantization accuracy. This can be achieved by producing m amplified analog signals with amplifications 2(i−1)k where k=constant and i=1, 2, . . . m. The largest linearly amplified signal will be selected by a logic circuit (after sampling) and converted into an n-bit digital data code by an A/D converter. In the same time, the logic circuit produces an m-bit logic flag code. The n-bit data code (u), the m-bit logic flag code (v) and the constant k are combined to form a final digital output uvk with n+(m−1)k bits. In this way, the resolution and dynamic range can be designed independently. Unlike the know logarithmic amplifier solution, the floating-point A/D converter give a linear digital code output directly without using any look-up table.Type: GrantFiled: August 18, 1999Date of Patent: November 13, 2001Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventor: Jiren Yuan
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Patent number: 5585796Abstract: An analog-to-digital arrangement for A/D converting a high-frequency analog input signal into a series of digital signals on-line with high sampling rate. It includes several computing channels for providing a digital signal from an analog input, each including a sample-and-hold means, to which the analog input signal is connected, a multiplexing means having several inputs, each input being connected to an individual computing channel output, and, a timing circuit controlling cyclically in a clock signal rate and in a prescribed order one at the time of the sample-and-hold means to hold the current analog value of the analog input signal and also to control the multiplexing means to place on its output one at the time of the digital outputs of the several computing channels. All the computing channels compute the digital value of the analog value held in its sample-and-hold means during a digitizing phase simultaneously but skewed in relation to the other computing channels.Type: GrantFiled: September 19, 1994Date of Patent: December 17, 1996Inventors: Christer M. Svensson, Jiren Yuan