Abstract: A test circuit for stimulating the inputs of preprogrammed logic circuits, having a pulse input terminal connected to one of the inputs of a NAND circuit. The output of the NAND circuit is connected via a first resistor to the base of a first switching PNP transistor, the emitter of which is connected to a first positive voltage supply terminal and the collector of which is connected to the collector of a second switching NPN transistor. The base of the second NPN transistor is connected both through a fourth resistor to an earth terminal of the circuit system and through a third resistor and a second resistor to a second positive voltage supply terminal and the emitter of which is connected both through a fifth resistor to the earth terminal of the circuit system and to an output terminal. The output terminal is connected to a measuring point or probe which is connected to the input of the connected-up logic circuit.