Abstract: According to one embodiment, a circuit design device includes a classification unit and a generation unit. The classification unit is configured to classify a plurality of wires included in a circuit into a first wire group that includes at least one first wire and a second wire group that includes at least one second wire based on toggle rates of the plurality of wires. The generation unit is configured to generate, based on first information indicating a layout of the plurality of wires on a substrate, second information indicating a layout of the plurality of wires on the substrate and a first dummy wire, the first dummy wire being arranged in a first region within a first range from the first wire.

Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, an interconnection structure provided on a first principal surface of the semiconductor substrate and including first interconnection layers electrically connected to the peripheral circuit area, a second interconnection layer provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a third interconnection layer provided above the second interconnection layer with an insulating layer therebetween, and through electrodes electrically connecting the second interconnection layer to the third interconnection layer.

Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, an interconnection structure provided on a first principal surface of the semiconductor substrate and including first interconnection layers electrically connected to the peripheral circuit area, a second interconnection layer provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a third interconnection layer provided above the second interconnection layer with an insulating layer therebetween, and through electrodes electrically connecting the second interconnection layer to the third interconnection layer.

Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, a first line provided in the peripheral circuit area and on a first principal surface of the semiconductor substrate, a second line provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a first through electrode connected to one end of the first line and one end of the second line and passing through the semiconductor substrate, and a second through electrode connected to the other end of the first line and the other end of the second line and passing through the semiconductor substrate.

Abstract: In general, according to one embodiment, a designing apparatus includes a clock tree generator, a logic modifier, a layout modifier, and an outputting module. The clock tree generator is configured to generate a clock tree. The logic modifier is configured to logically insert a delay element in such a manner that a hold violation is modified without considering a setup timing with respect to circuit data corresponding to the clock tree generated by the clock tree generator. The layout modifier is configured to modify a layout of a semiconductor integrated circuit based on a processing result of the logic modifier. The outputting module is configured to output the layout of the semiconductor integrated circuit. The layout is modified by the layout modifier.