Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic suicide layer.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: A semiconductor device and a manufacturing method for a hyperfine structure wherein contact of a gate electrode with a side-wall composed of a silicon nitride layer within a contact hole due to an alignment deviation may be prevented. The semiconductor device is structured such that the contact hole is formed in an inter-layer insulating layer and the side-wall is formed along a wall surface within the contact hole. A bottom of the side-wall is composed of a silicon oxide layer or a silicon oxide nitride layer, and an upper portion of the side-wall is formed of a silicon nitride layer.

Abstract: A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacent to one bit line in the second pair for one part of its length, and adjacent to the other bit line in the second pair for another part of its length. Coupling noise is thereby neutralized. Data-inverting circuitry is provided to compensate for the inversion of data that results from the cross-over of the bit lines. According to a second aspect of the invention, the two complementary pairs of bit lines are placed in separate interconnecting layers, to reduce coupling noise by reducing the capacitive coupling between the bit lines.

Abstract: A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacent to one bit line in the second pair for one part of its length, and adjacent to the other bit line in the second pair for another part of its length. Coupling noise is thereby neutralized. Data-inverting circuitry is provided to compensate for the inversion of data that results from the cross-over of the bit lines. According to a second aspect of the invention, the two complementary pairs of bit lines are placed in separate interconnecting layers, to reduce coupling noise by reducing the capacitive coupling between the bit lines.