Abstract: A storage control apparatus contains plural request stacks for storing the access request; a stack selecting circuit for selecting a request stack by accepting the access requests one after another and for storing the access request; and a priority determining circuit for selecting the access request stored in said request stack in order of priority and makes access to a main storage unit in response to an access request from an input-output processor, instruction processor and the like. When memory access requests are issued continuously from the unit as a source of issuing the same access request to the storage control apparatus, the access request which follows can make access to a cache memory while the previous request is making access to the main storage unit, thereby preventing a reduction in a total throughput.

Abstract: A data processing system which encludes an instruction processor, a storage controller, a main storage, and an extended storage. The storage controller contains a data transfer unit for transferring data between the main storage and the extended storage by an instruction from the instruction process specifying an amount of the data to be transferred. The data transfer unit is provided in the storage controller and with a data buffer and an address addition-subtraction circuit for operating a source address and a destination address. The data is transferred between the main storage and the extended storage by sending to a firmware of a storage control a main storage real address translated from a main storage virtual address specified by the instruction, the number of data to be transferred from the main storage, an extended storage real address, and the number of bytes to be transferred from the extended storage, in a manner so as to match with a unit of data to be processed on the extended storage.

Abstract: In a multiprocessor system in which a plurality of instruction processors (IP's) share a main storage (MS) and a channel controller (CHC) through a system controller (SC), when an I/O interrupt request is issued, IP's connected to the SC are examined to determine whether each of the IP's is executing an instruction which permits acceptance of the I/O interrupt request during the execution of the instruction. If one of the IP's is not executing such an instruction and can accept the I/O interrupt request, that IP will be selected.

Abstract: An apparatus for controlling interrupts is provided in a system controller SC of a multiprocessor system in which a plurality of instruction processors IP share a main storage MS and a channel controller CHC through the system controller SC. The apparatus for controlling interrupts holds I/O interrupt control data for each of the instruction processors IP, and selects the most suitable instruction processor IP to process an I/O interrupt, without receiving responses from all of the instruction processors IP.