Abstract: A data processor of this invention capable of extending the expressible range of constant data in which a portion of the expressible range not necessary for an instruction is removed from that range and the vacancy thus made is utilized for extending the range of data necessary for the instruction.

Abstract: A test circuit which utilizes a multi-bit impact signature register and an additional register coupled to the output of the signature register and configured as a linear feedback multi-stage shift register. The total number of stages in the two registers is larger than the width of the test data (number of bits) to be input. A single feedback loop couples the output of the last additional register stage back to the first stage of the signature register. Each bit of the test data is input to an exclusive-or element at the input to each stage of the shift register and is exclusive-or-operated sequentially with the result of an exclusive-or operation stored in the preceding stage, and the result of the operation in the last stage is fed from the additional register back to the first-stage exclusive-or- element of the signature register with a delay.