Patents by Inventor Jiro Oshima

Jiro Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130644
    Abstract: A plasma processing apparatus includes: a chamber including a first member, and a second member detachable from the first member; a conductive member disposed between the first member and the second member; and a first high frequency power supply generating plasma in the chamber. The conductive member includes a resin member made of a resin material, and a metal film covering a surface of the resin member.
    Type: Application
    Filed: March 13, 2020
    Publication date: April 28, 2022
    Applicants: Noa Leading Co., Ltd., TOSHIBA MATERIALS CO., LTD.
    Inventors: Masahiro YOKOTA, Akihiko HAPPOYA, Ken TAKAHASHI, Shusuke MORITA, Jiro OSHIMA, Shuichi SAITO, Noriaki YAGI, Atsuya SASAKI
  • Patent number: 4910170
    Abstract: In the invention, the width of the emitter contact layer is determined in accordance with the width of a first side wall, and the junction distance between a base contact layer and the emitter contact layer is determined in accordance with the width of a second side wall. The junction distance between the emitter contact layer and the base contact layer can be decreased, no extra high-temperature annealing such as thermal oxidation is needed, and the diffusion profile can be controlled to be shallow.
    Type: Grant
    Filed: February 23, 1988
    Date of Patent: March 20, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyo Motozima, Shin-ichi Taka, Jiro Oshima
  • Patent number: 4403392
    Abstract: A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask l
    Type: Grant
    Filed: May 22, 1980
    Date of Patent: September 13, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Jiro Oshima, Masaharu Aoyama, Seiji Yasuda, Toshio Yonezawa