Patents by Inventor Jiro Shimbo
Jiro Shimbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11635845Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.Type: GrantFiled: September 29, 2020Date of Patent: April 25, 2023Assignee: Synaptics Japan GKInventors: Makoto Takeuchi, Shigeru Ota, Atsushi Shikata, Kentaro Suzuki, Jiro Shimbo
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Patent number: 11212424Abstract: A display driver comprises drop amount calculation circuitry and digital gamma correction circuitry. The drop amount calculation circuitry is configured to calculate a drop amount of a power source voltage supplied to a display panel from a setting value. The digital gamma correction circuitry is configured to perform digital gamma correction on an input image data based on the drop amount.Type: GrantFiled: September 25, 2019Date of Patent: December 28, 2021Assignee: Synaptics IncorporatedInventors: Satoshi Saito, Kei Miyazawa, Hidefumi Odate, Jiro Shimbo, Kazuyuki Tanimoto
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Patent number: 11194420Abstract: A processing system comprises interface circuitry and a timing controller. The interface circuitry is configured to receive a vertical sync period indicator that indicates a start of an external vertical sync period. The timing controller is configured to, in response to a change in a display frame rate, control timing of a display drive operation and a proximity sensing operation to maintain a proximity sensing frame rate based on input timing of the vertical sync period indicator to the interface circuitry. The processing system is configured to supply drive signals to display elements of a display panel in the display drive operation and acquire sensing signals from sensor electrodes of the display panel in the proximity sensing operation.Type: GrantFiled: November 19, 2019Date of Patent: December 7, 2021Assignee: Synaptics IncorporatedInventors: Atsushi Shikata, Shigeru Ota, Makoto Takeuchi, Jiro Shimbo, Kentaro Suzuki
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Publication number: 20210149540Abstract: A processing system comprises interface circuitry and a timing controller. The interface circuitry is configured to receive a vertical sync period indicator that indicates a start of an external vertical sync period. The timing controller is configured to, in response to a change in a display frame rate, control timing of a display drive operation and a proximity sensing operation to maintain a proximity sensing frame rate based on input timing of the vertical sync period indicator to the interface circuitry. The processing system is configured to supply drive signals to display elements of a display panel in the display drive operation and acquire sensing signals from sensor electrodes of the display panel in the proximity sensing operation.Type: ApplicationFiled: November 19, 2019Publication date: May 20, 2021Inventors: Atsushi SHIKATA, Shigeru OTA, Makoto TAKEUCHI, Jiro SHIMBO, Kentaro SUZUKI
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Publication number: 20210011575Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.Type: ApplicationFiled: September 29, 2020Publication date: January 14, 2021Inventors: Makoto TAKEUCHI, Shigeru OTA, Atsushi SHIKATA, Kentaro SUZUKI, Jiro SHIMBO
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Patent number: 10802645Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.Type: GrantFiled: September 13, 2018Date of Patent: October 13, 2020Assignee: Synaptics Japan GKInventors: Makoto Takeuchi, Shigeru Ota, Atsushi Shikata, Kentaro Suzuki, Jiro Shimbo
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Patent number: 10643515Abstract: A display driver includes: a memory comprising a plurality of memory regions each configured to store image data for one line of an image displayed in a frame; and control circuitry configured to adjust a number of in-use memory regions of the plurality of memory regions used to store the image data. The control circuitry is further configured to control the memory so that image data for respective lines of the image are cyclically stored in the in-use memory regions in a fixed order.Type: GrantFiled: September 20, 2018Date of Patent: May 5, 2020Assignee: Synaptics Japan GKInventors: Kentaro Suzuki, Atsushi Shikata, Jiro Shimbo, Makoto Takeuchi, Shigeru Ota
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Publication number: 20200112654Abstract: A display driver comprises drop amount calculation circuitry and digital gamma correction circuitry. The drop amount calculation circuitry is configured to calculate a drop amount of a power source voltage supplied to a display panel from a setting value. The digital gamma correction circuitry is configured to perform digital gamma correction on an input image data based on the drop amount.Type: ApplicationFiled: September 25, 2019Publication date: April 9, 2020Inventors: Satoshi SAITO, Kei MIYAZAWA, Hidefumi ODATE, Jiro SHIMBO, Kazuyuki TANIMOTO
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Publication number: 20190096309Abstract: A display driver includes: a memory comprising a plurality of memory regions each configured to store image data for one line of an image displayed in a frame; and control circuitry configured to adjust a number of in-use memory regions of the plurality of memory regions used to store the image data. The control circuitry is further configured to control the memory so that image data for respective lines of the image are cyclically stored in the in-use memory regions in a fixed order.Type: ApplicationFiled: September 20, 2018Publication date: March 28, 2019Inventors: Kentaro SUZUKI, Atsushi SHIKATA, Jiro SHIMBO, Makoto TAKEUCHI, Shigeru OTA
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Publication number: 20190095033Abstract: A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.Type: ApplicationFiled: September 13, 2018Publication date: March 28, 2019Inventors: Makoto Takeuchi, Shigeru Ota, Atsushi Shikata, Kentaro Suzuki, Jiro Shimbo
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Patent number: 8638142Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: GrantFiled: September 14, 2012Date of Patent: January 28, 2014Assignee: Renesas Electronics CorporationInventors: Ryo Endo, Jiro Shimbo, Tomomitsu Kitamura
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Publication number: 20130009681Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo ENDO, Jiro SHIMBO, Tomomitsu KITAMURA
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Patent number: 8299828Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: GrantFiled: May 4, 2012Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Ryo Endo, Jiro Shimbo, Tomomitsu Kitamura
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Publication number: 20120212266Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: ApplicationFiled: May 4, 2012Publication date: August 23, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo ENDO, Jiro SHIMBO, Tomomitsu KITAMURA
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Patent number: 8207767Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: GrantFiled: November 29, 2010Date of Patent: June 26, 2012Assignee: Renesas Electronics CorporationInventors: Ryo Endo, Jiro Shimbo, Tomomitsu Kitamura
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Publication number: 20110140747Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.Type: ApplicationFiled: November 29, 2010Publication date: June 16, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryo ENDO, Jiro SHIMBO, Tomomitsu KITAMURA
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Patent number: 7647033Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.Type: GrantFiled: January 24, 2007Date of Patent: January 12, 2010Assignee: Renesas Technology Corp.Inventors: Toshiya Uozumi, Jiro Shimbo
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Publication number: 20070236297Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.Type: ApplicationFiled: January 24, 2007Publication date: October 11, 2007Inventors: Toshiya UOZUMI, Jiro Shimbo