Patents by Inventor Jiro YOTA
Jiro YOTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830826Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.Type: GrantFiled: June 27, 2022Date of Patent: November 28, 2023Assignee: Skyworks Solutions, Inc.Inventors: Jiro Yota, Shiban Kishan Tiku
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Patent number: 11804460Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.Type: GrantFiled: February 21, 2022Date of Patent: October 31, 2023Assignee: Skyworks Solutions, Inc.Inventors: Jiro Yota, Dogan Gunes
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Publication number: 20220336396Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.Type: ApplicationFiled: February 21, 2022Publication date: October 20, 2022Inventors: Jiro YOTA, Dogan GUNES
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Publication number: 20220328428Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.Type: ApplicationFiled: June 27, 2022Publication date: October 13, 2022Inventors: Jiro Yota, Shiban Kishan Tiku
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Patent number: 11387193Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.Type: GrantFiled: December 30, 2020Date of Patent: July 12, 2022Assignee: Skyworks Solutions, Inc.Inventors: Jiro Yota, Shiban Kishan Tiku
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Patent number: 11335669Abstract: A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.Type: GrantFiled: November 14, 2019Date of Patent: May 17, 2022Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Patent number: 11257774Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.Type: GrantFiled: August 28, 2015Date of Patent: February 22, 2022Assignee: Skyworks Solutions, Inc.Inventors: Jiro Yota, Dogan Gunes
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Patent number: 11222855Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.Type: GrantFiled: August 13, 2020Date of Patent: January 11, 2022Assignee: Skyworks Solutions, Inc.Inventors: Jiro Yota, Shiban Kishan Tiku
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Patent number: 11101160Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.Type: GrantFiled: April 10, 2020Date of Patent: August 24, 2021Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Publication number: 20210118820Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Inventors: Jiro Yota, Shiban Kishan Tiku
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Publication number: 20210118821Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and one or more polyimide layers disposed over the substrate. Each polyimide layer can have a trench that separates a first portion of the polyimide layer that is adjacent a metal layer from a second portion of the polyimide layer. The trench(es) can be formed by etching the polyimide layer(s). A topcoat insulation layer can be disposed over the polyimide layers, a portion of the topcoat insulation layer disposed over the trench(es) define a moat. The topcoat insulation layer is impervious to moisture and the moat inhibits moisture from traveling along the one or more polymer interlevel dielectric layers from the second portion to the first portion.Type: ApplicationFiled: December 30, 2020Publication date: April 22, 2021Inventors: Jiro Yota, Shiban Kishan Tiku
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Publication number: 20210074652Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.Type: ApplicationFiled: August 13, 2020Publication date: March 11, 2021Inventors: Jiro Yota, Shiban Kishan Tiku
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Publication number: 20210020587Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and one or more polyimide layers disposed over the substrate. Each polyimide layer can have a trench that separates a first portion of the polyimide layer that is adjacent a metal layer from a second portion of the polyimide layer. The trench(es) can be formed by etching the polyimide layer(s). A topcoat insulation layer can be disposed over the polyimide layers, a portion of the topcoat insulation layer disposed over the trench(es) define a moat. The topcoat insulation layer is impervious to moisture and the moat inhibits moisture from traveling along the one or more polymer interlevel dielectric layers from the second portion to the first portion.Type: ApplicationFiled: June 2, 2020Publication date: January 21, 2021Inventors: Jiro Yota, Shiban Kishan Tiku
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Publication number: 20200243369Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Patent number: 10629468Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.Type: GrantFiled: February 10, 2017Date of Patent: April 21, 2020Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Publication number: 20200083202Abstract: A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Patent number: 10483248Abstract: An electronics package includes a semiconductor substrate having one or more passive devices formed thereon and a cavity defined in a first surface thereof. A piezoelectric substrate is bonded to the semiconductor substrate and has a radio frequency (RF) filter formed thereon. The RF filter is disposed within the cavity defined in the semiconductor substrate.Type: GrantFiled: March 6, 2018Date of Patent: November 19, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Publication number: 20180277527Abstract: An electronics package includes a semiconductor substrate having one or more passive devices formed thereon and a cavity defined in a first surface thereof. A piezoelectric substrate is bonded to the semiconductor substrate and has a radio frequency (RF) filter formed thereon. The RF filter is disposed within the cavity defined in the semiconductor substrate.Type: ApplicationFiled: March 6, 2018Publication date: September 27, 2018Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Publication number: 20170236742Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.Type: ApplicationFiled: February 10, 2017Publication date: August 17, 2017Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
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Publication number: 20160064811Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.Type: ApplicationFiled: August 28, 2015Publication date: March 3, 2016Inventors: Jiro YOTA, Dogan GUNES