Patents by Inventor Jirou Miura
Jirou Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8361861Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.Type: GrantFiled: January 19, 2012Date of Patent: January 29, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Jirou Miura
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Patent number: 8227337Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.Type: GrantFiled: December 20, 2010Date of Patent: July 24, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
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Publication number: 20120115252Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.Type: ApplicationFiled: January 19, 2012Publication date: May 10, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Jirou MIURA
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Patent number: 8124476Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.Type: GrantFiled: September 3, 2009Date of Patent: February 28, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Jirou Miura
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Publication number: 20110086508Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.Type: ApplicationFiled: December 20, 2010Publication date: April 14, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
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Patent number: 7880302Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.Type: GrantFiled: February 21, 2008Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
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Publication number: 20100022031Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.Type: ApplicationFiled: September 3, 2009Publication date: January 28, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Jirou Miura
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Patent number: 7507621Abstract: Provided is a method of manufacturing a semiconductor device including the steps of: forming a first insulating film on a silicon substrate; forming a capacitor in which a lower electrode, a capacitor dielectric film configured of ferroelectric material, and an upper electrode are laminated in this order on the first insulating film; forming a silicon nitride film by a catalytic CVD method as a first capacitor protect insulating film covering the capacitor and the first insulating film; and forming a second insulating film on the first capacitor protect insulating film.Type: GrantFiled: January 3, 2006Date of Patent: March 24, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Jirou Miura
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Patent number: 7498625Abstract: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact holes (21) are formed in the interlayer insulating film (18). In other words, gaps (notches) are formed in the bottom electrode (15) between lower ends of at least two of the contact holes (21). And a wiring (25) connected to the bottom electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).Type: GrantFiled: December 15, 2005Date of Patent: March 3, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Tomohiro Takamatsu, Jirou Miura, Mitsuhiro Nakamura, Hirotoshi Tachibana, Genichi Komuro
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Publication number: 20080197502Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.Type: ApplicationFiled: February 21, 2008Publication date: August 21, 2008Applicant: FUJITSU LIMITEDInventors: Hideaki KIKUCHI, Kouichi NAGAI, Jirou MIURA
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Publication number: 20070184595Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.Type: ApplicationFiled: March 23, 2007Publication date: August 9, 2007Applicant: FUJITSU LIMITEDInventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
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Patent number: 7211850Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.Type: GrantFiled: June 4, 2004Date of Patent: May 1, 2007Assignee: Fujitsu LimitedInventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
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Publication number: 20070090438Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.Type: ApplicationFiled: January 25, 2006Publication date: April 26, 2007Applicant: FUJITSU LIMITEDInventor: Jirou Miura
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Publication number: 20070048963Abstract: Provided is a method of manufacturing a semiconductor device including the steps of: forming a first insulating film on a silicon substrate; forming a capacitor in which a lower electrode, a capacitor dielectric film configured of ferroelectric material, and an upper electrode are laminated in this order on the first insulating film; forming a silicon nitride film by a catalytic CVD method as a first capacitor protect insulating film covering the capacitor and the first insulating film; and forming a second insulating film on the first capacitor protect insulating film.Type: ApplicationFiled: January 3, 2006Publication date: March 1, 2007Applicant: FUJITSU LIMITEDInventor: Jirou Miura
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Publication number: 20060091438Abstract: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact holes (21) are formed in the interlayer insulating film (18). In other words, gaps (notches) are formed in the bottom electrode (15) between lower ends of at least two of the contact holes (21). And a wiring (25) connected to the bottom electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).Type: ApplicationFiled: December 15, 2005Publication date: May 4, 2006Applicant: FUJITSU LIMITEDInventors: Tomohiro Takamatsu, Jirou Miura, Mitsuhiro Nakamura, Hirotoshi Tachibana, Genichi Komuro
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Patent number: 6913970Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: GrantFiled: November 26, 2002Date of Patent: July 5, 2005Assignee: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Publication number: 20050072998Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.Type: ApplicationFiled: June 4, 2004Publication date: April 7, 2005Applicant: FUJITSU LIMITEDInventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
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Publication number: 20030080364Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: ApplicationFiled: November 26, 2002Publication date: May 1, 2003Applicant: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Patent number: 6509593Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: GrantFiled: December 29, 2000Date of Patent: January 21, 2003Assignee: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
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Publication number: 20020011616Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.Type: ApplicationFiled: December 29, 2000Publication date: January 31, 2002Applicant: Fujitsu LimitedInventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki