Patents by Inventor Jirou Miura

Jirou Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8361861
    Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 29, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Jirou Miura
  • Patent number: 8227337
    Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: July 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
  • Publication number: 20120115252
    Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.
    Type: Application
    Filed: January 19, 2012
    Publication date: May 10, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Jirou MIURA
  • Patent number: 8124476
    Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Jirou Miura
  • Publication number: 20110086508
    Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.
    Type: Application
    Filed: December 20, 2010
    Publication date: April 14, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
  • Patent number: 7880302
    Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: February 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideaki Kikuchi, Kouichi Nagai, Jirou Miura
  • Publication number: 20100022031
    Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.
    Type: Application
    Filed: September 3, 2009
    Publication date: January 28, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Jirou Miura
  • Patent number: 7507621
    Abstract: Provided is a method of manufacturing a semiconductor device including the steps of: forming a first insulating film on a silicon substrate; forming a capacitor in which a lower electrode, a capacitor dielectric film configured of ferroelectric material, and an upper electrode are laminated in this order on the first insulating film; forming a silicon nitride film by a catalytic CVD method as a first capacitor protect insulating film covering the capacitor and the first insulating film; and forming a second insulating film on the first capacitor protect insulating film.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: March 24, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Jirou Miura
  • Patent number: 7498625
    Abstract: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact holes (21) are formed in the interlayer insulating film (18). In other words, gaps (notches) are formed in the bottom electrode (15) between lower ends of at least two of the contact holes (21). And a wiring (25) connected to the bottom electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: March 3, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomohiro Takamatsu, Jirou Miura, Mitsuhiro Nakamura, Hirotoshi Tachibana, Genichi Komuro
  • Publication number: 20080197502
    Abstract: A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 21, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki KIKUCHI, Kouichi NAGAI, Jirou MIURA
  • Publication number: 20070184595
    Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
    Type: Application
    Filed: March 23, 2007
    Publication date: August 9, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
  • Patent number: 7211850
    Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: May 1, 2007
    Assignee: Fujitsu Limited
    Inventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
  • Publication number: 20070090438
    Abstract: Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film.
    Type: Application
    Filed: January 25, 2006
    Publication date: April 26, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Jirou Miura
  • Publication number: 20070048963
    Abstract: Provided is a method of manufacturing a semiconductor device including the steps of: forming a first insulating film on a silicon substrate; forming a capacitor in which a lower electrode, a capacitor dielectric film configured of ferroelectric material, and an upper electrode are laminated in this order on the first insulating film; forming a silicon nitride film by a catalytic CVD method as a first capacitor protect insulating film covering the capacitor and the first insulating film; and forming a second insulating film on the first capacitor protect insulating film.
    Type: Application
    Filed: January 3, 2006
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Jirou Miura
  • Publication number: 20060091438
    Abstract: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact holes (21) are formed in the interlayer insulating film (18). In other words, gaps (notches) are formed in the bottom electrode (15) between lower ends of at least two of the contact holes (21). And a wiring (25) connected to the bottom electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).
    Type: Application
    Filed: December 15, 2005
    Publication date: May 4, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Tomohiro Takamatsu, Jirou Miura, Mitsuhiro Nakamura, Hirotoshi Tachibana, Genichi Komuro
  • Patent number: 6913970
    Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
  • Publication number: 20050072998
    Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.
    Type: Application
    Filed: June 4, 2004
    Publication date: April 7, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Jirou Miura, Mitsushi Fujiki, Aki Dote, Tomohiro Takamatsu
  • Publication number: 20030080364
    Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Application
    Filed: November 26, 2002
    Publication date: May 1, 2003
    Applicant: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
  • Patent number: 6509593
    Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 21, 2003
    Assignee: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
  • Publication number: 20020011616
    Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Application
    Filed: December 29, 2000
    Publication date: January 31, 2002
    Applicant: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki