Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

Abstract: A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.

Abstract: A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.

Abstract: A semiconductor device capable of compensating for an electrical characteristic variation of a transistor array is provided. The semiconductor device includes an N-well region and a transistor array spaced from the N-well region and including a plurality of transistors. A characteristic of each of the transistors is adjusted to enable the transistors to have a same electrical characteristic.

Abstract: A method for estimating statistical distribution characteristics of physical parameters of a semiconductor device includes manufacturing a plurality of semiconductor device chips, each having a plurality of transistors, preparing electrical characteristic data by measuring electrical characteristics of the plurality of transistors included in the plurality of chips, extracting an inter-chip distribution characteristic and an intra-chip distribution characteristic of the electrical characteristics by analyzing the electrical characteristic data, generating random number data satisfying the extracted inter-chip and intra-chip distribution characteristics, and performing a simulation for extracting statistical distribution characteristic data of the physical parameters of the chips, based on the random number data.

Abstract: A method for estimating statistical distribution characteristics of physical parameters of a semiconductor device includes manufacturing a plurality of semiconductor device chips, each having a plurality of transistors, preparing electrical characteristic data by measuring electrical characteristics of the plurality of transistors included in the plurality of chips, extracting an inter-chip distribution characteristic and an intra-chip distribution characteristic of the electrical characteristics by analyzing the electrical characteristic data, generating random number data satisfying the extracted inter-chip and intra-chip distribution characteristics, and performing a simulation for extracting statistical distribution characteristic data of the physical parameters of the chips, based on the random number data.