Patents by Inventor Jishen Zhao
Jishen Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10572378Abstract: Dynamic memory expansion based on data compression is described. Data represented in at least one page to be written to a main memory of a computing device is received. The data is compressed in the at least one page to generate at least one compressed physical page and a metadata entry corresponding to each page of the at least one compressed physical page. The metadata entry is cached in a metadata cache including metadata entries and pointers to the uncompressed region of the at least one compressed physical page.Type: GrantFiled: March 20, 2014Date of Patent: February 25, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Sheng Li, Jichuan Chang, Jishen Zhao
-
Patent number: 10303622Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.Type: GrantFiled: March 6, 2015Date of Patent: May 28, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Rajeev Balasubramonian, Naveen Muralimanohar, Gregg B. Lesartre, Paolo Faraboschi, Jishen Zhao
-
Patent number: 10254988Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.Type: GrantFiled: March 12, 2015Date of Patent: April 9, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Rajeev Balasubramonian, Gregg B. Lesartre, Robert Schreiber, Jishen Zhao, Naveen Muralimanohar, Paolo Faraboschi
-
Patent number: 10241711Abstract: Example methods and systems to provide persistent memory are disclosed herein. An example system includes a nonvolatile cache to store data received from a volatile cache. The data is associated with a transaction and the data is to be identified as durable when the transaction is committed. The example system includes a nonvolatile memory to store the data received from the nonvolatile cache when the data is identified as durable.Type: GrantFiled: March 14, 2013Date of Patent: March 26, 2019Assignee: HEWLETT-PACKARD ENTERPRISE DEVELOPMENT LPInventors: Doe Hyun Yoon, Sheng Li, Jishen Zhao, Norman P. Jouppi
-
Patent number: 10152247Abstract: A technique includes acquiring a plurality of write requests from at least one memory controller and logging information associated with the plurality of write requests in persistent storage. The technique includes applying the plurality of write requests atomically as a group to persistent storage.Type: GrantFiled: January 23, 2014Date of Patent: December 11, 2018Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Sheng Li, Jishen Zhao, Jichuan Chang, Parthasarathy Ranganathan, Alistair Veitch, Kevin T. Lim, Mark Lillibridge
-
Patent number: 10019363Abstract: Example implementations may relate to a version controller allocating a copy page in persistent memory upon receiving, from an application executing on a processor, a copy command to version an image page for an atomic transaction. The version controller may receive application data addressed to a cache line of the image page, and may write the application data to a cache line of the copy page corresponding to the addressed cache line of the image page. If the version controller receives a replace-type transaction commit command, the version controller may generate a final page by either forward merging the image page into the copy page or backward merging the copy page into the image page, depending a merge direction policy.Type: GrantFiled: April 3, 2015Date of Patent: July 10, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Douglas L. Voigt, Charles B. Morrey, III, Jishen Zhao, Dhruva Chakrabarti, Joseph E. Foster
-
Publication number: 20180074959Abstract: According to an example, a node-based computing device includes memory nodes communicatively coupled to a processor node. The memory nodes may form a main memory address space for the processor node. The processor node may establish a virtual circuit through memory nodes. The virtual circuit may dedicate a path within the memory nodes. The processor node may then communicate a message through the virtual circuit. The memory nodes may forward the message according to the path dedicated by the virtual circuit.Type: ApplicationFiled: July 22, 2014Publication date: March 15, 2018Inventors: Sheng Li, Jishen Zhao, Kevin T. Lim, Paolo Faraboschi
-
Publication number: 20170286297Abstract: Example implementations may relate to a version controller allocating a copy page in persistent memory upon receiving, from an application executing on a processor, a copy command to version an image page for an atomic transaction. The version controller may receive application data addressed to a cache line of the image page, and may write the application data to a cache line of the copy page corresponding to the addressed cache line of the image page. If the version controller receives a replace-type transaction commit command, the version controller may generate a final page by either forward merging the image page into the copy page or backward merging the copy page into the image page, depending a merge direction policy.Type: ApplicationFiled: April 3, 2015Publication date: October 5, 2017Inventors: Douglas L. Voigt, Charles B. MORREY, III, Jishen ZHAO, Dhruva CHAKRABARTI, Joseph E. FOSTER
-
Publication number: 20170220257Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.Type: ApplicationFiled: March 12, 2015Publication date: August 3, 2017Inventors: Rajeev Balasubramonian, Gregg B. Lesartre, Robert Schreiber, Jishen Zhao, Naveen Muralimanohar, Paolo Faraboschi
-
Publication number: 20170220488Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.Type: ApplicationFiled: March 6, 2015Publication date: August 3, 2017Inventors: Rajeev Balasubramonian, Naveen Muralimanohar, Gregg B. Lesartre, Paolo Faraboschi, Jishen Zhao
-
Publication number: 20170004069Abstract: Dynamic memory expansion based on data compression is described. Data represented in at least one page to be written to a main memory of a computing device is received. The data is compressed in the at least one page to generate at least one compressed physical page and a metadata entry corresponding to each page of the at least one compressed physical page. The metadata entry is cached in a metadata cache deluding metadata entries and pointers to the uncompressed region of the at least one compressed physical page.Type: ApplicationFiled: March 20, 2014Publication date: January 5, 2017Applicant: Hewlett Packard Enterprise Development LPInventors: Sheng Li, Jichuan Chang, Jishen Zhao
-
Publication number: 20160342351Abstract: A technique includes acquiring a plurality of write requests from at least one memory controller and logging information associated with the plurality of write requests in persistent storage. The technique includes applying the plurality of write requests atomically as a group to persistent storage.Type: ApplicationFiled: January 23, 2014Publication date: November 24, 2016Inventors: Sheng Li, Jishen Zhao, Jichuan Chang, Parthasarathy Ranganathan, Alistair Veitch, Kevin T. Lim, Mark Lillibridge
-
Publication number: 20160267015Abstract: A method for mapping virtual memory pages to physical memory pages is described. The method includes receiving a mapping of a virtual memory page to multiple physical memory pages, detecting a request for a transaction to be performed on data contained in the multiple physical memory pages, in which the transaction includes a number of data updates, determining which of the number of multiple physical memory pages contains a latest version of the data to be updated by the transaction, updating a physical memory page by performing the transaction within a physical memory page among the multiple physical memory pages that does not contain the latest version of the data, and updating an indication of which of the physical memory pages contains the latest version of the data pertaining to the transaction.Type: ApplicationFiled: October 29, 2013Publication date: September 15, 2016Inventors: Sheng Li, Jishen Zhao, Jichuan Chang, Parthasarathy Ranganathan, Alistair Veitch, Kevin T. Lim
-
Publication number: 20160034225Abstract: Example methods and systems to provide persistent memory are disclosed herein. An example system includes a nonvolatile cache to store data received from a volatile cache. The data is associated with a transaction and the data is to be identified as durable when the transaction is committed. The example system includes a nonvolatile memory to store the data received from the nonvolatile cache when the data is identified as durable.Type: ApplicationFiled: March 14, 2013Publication date: February 4, 2016Inventors: Doe Hyun Yoon, Sheng Li, Jishen Zhao, Norman P. Jouppi