Abstract: An integrated circuit device includes: a lower insulating film arranged on a substrate; a lower metal wiring layer passing through the lower insulating film; an upper insulating film arranged on the lower insulating film and the lower metal wiring layer; an upper metal wiring layer arranged on the upper insulating film; and a conductive contact plug passing through the upper insulating film in a vertical direction and disposed between the lower metal wiring layer and the upper metal wiring layer, wherein a first center of an uppermost portion farthest from the substrate, of the conductive contact plug, is shifted in a first direction, which is parallel to a main surface of the substrate, from a second center of a lowermost portion closest to the substrate, of the conductive contact plug.

Abstract: A wiring structure includes: a first wiring disposed on a substrate, wherein the first wiring includes a first extension portion that extends in a first direction and has a first width in a second direction, and a first expansion portion that is formed at a first end portion of end portions of the first extension portion and has a first maximum width, wherein the first maximum width is larger than the first width; and a second wiring disposed on the substrate, wherein the second wiring extends in the first direction and faces the first expansion portion of the first wiring, wherein a first end portion of end portions of the second wiring facing the first expansion portion has a second maximum width, wherein the second maximum width is substantially the same as the first maximum width.

Abstract: Provided is a semiconductor device including a lower structure, a dielectric layer on the lower structure, and first and second interconnection lines extending in a first direction in the dielectric layer and alternately disposed and spaced apart from each other in a second direction, perpendicular to the first direction, at least one of the first interconnection lines includes a first subpattern and a second subpattern overlapping in the first direction and spaced apart from each other, at least one of the second interconnection lines includes a third subpattern and a fourth subpattern overlapping in the first direction and spaced apart from each other, two ends of the first subpattern and the second subpattern respectively facing each other in the first direction have a convex protruding shape, and two ends of the third subpattern and the fourth subpattern respectively facing each other in the first direction have a concave protruding shape.

Abstract: An integrated circuit device includes a substrate; a fin-type active region that extends in a first horizontal direction on the substrate; a gate line on the fin-type active region, wherein the gate line extends in a second horizontal direction that intersects the first horizontal direction; and a gate dielectric film that is in contact with a lower surface and opposite sidewalls of the gate line, wherein a gate upper surface of the gate line includes a portion that has a decreasing distance from the substrate in a vertical direction as a distance between the portion of the gate upper surface of the gate line and the gate dielectric film in the first horizontal direction decreases.

Abstract: Provided is a semiconductor device and method of manufacturing same.

Abstract: An etching gas composition includes an organic fluorine compound and tungsten fluoride.

Abstract: An etching gas composition includes an organic fluorine compound and carbon disulfide.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

Abstract: An ultrasonic suture device is provided for drilling arc shaped holes through hard materials, such as metals, glass, or bone. The ultrasonic suture device includes a transducer, horn and probe. The probe is constructed of three sections including a stem section, extension section and arc section. The stem section extends along the longitudinal axis of the ultrasonic suture device, while the arc section is constructed in the shape of an arc of a circle and is positioned concentrically with the stem's axis. At the distal extremity of the probe is a tip constructed for drilling into hard materials.

Abstract: An ultrasonic suture device is provided for drilling arc shaped holes through hard materials, such as metals, glass, or bone. The ultrasonic suture device includes a transducer, horn and probe. The probe is constructed of three sections including a stem section, extension section and arc section. The stem section extends along the longitudinal axis of the ultrasonic suture device, while the arc section is constructed in the shape of an arc of a circle and is positioned concentrically with the stem's axis. At the distal extremity of the probe is a tip constructed for drilling into hard materials.