Patents by Inventor Jisoo Oh
Jisoo Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10522401Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.Type: GrantFiled: January 2, 2019Date of Patent: December 31, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungwoo Myung, GeumJung Seong, Jisoo Oh, JinWook Lee, Dohyoung Kim, Yong-Ho Jeon
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Publication number: 20190157147Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.Type: ApplicationFiled: January 2, 2019Publication date: May 23, 2019Inventors: Sungwoo MYUNG, GeumJung SEONG, Jisoo OH, JinWook LEE, Dohyoung KIM, Yong-Ho JEON
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Patent number: 10186457Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.Type: GrantFiled: October 26, 2017Date of Patent: January 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungwoo Myung, GeumJung Seong, Jisoo Oh, JinWook Lee, Dohyoung Kim, Yong-Ho Jeon
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Patent number: 10043889Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.Type: GrantFiled: October 3, 2017Date of Patent: August 7, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: GeumJung Seong, JinWook Lee, Dohyoung Kim, Sungwoo Myung, Jisoo Oh, Yong-Ho Jeon
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Publication number: 20180061958Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.Type: ApplicationFiled: October 26, 2017Publication date: March 1, 2018Inventors: Sungwoo MYUNG, GeumJung SEONG, Jisoo OH, JinWook LEE, Dohyoung KIM, Yong-Ho JEON
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Publication number: 20180033867Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.Type: ApplicationFiled: October 3, 2017Publication date: February 1, 2018Inventors: GeumJung SEONG, JinWook LEE, Dohyoung KIM, Sungwoo MYUNG, Jisoo OH, Yong-Ho JEON
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Patent number: 9806166Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.Type: GrantFiled: January 9, 2017Date of Patent: October 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungwoo Myung, GeumJung Seong, Jisoo Oh, JinWook Lee, Dohyoung Kim, Yong-Ho Jeon
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Patent number: 9806168Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.Type: GrantFiled: January 6, 2016Date of Patent: October 31, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: GeumJung Seong, JinWook Lee, Dohyoung Kim, Sungwoo Myung, Jisoo Oh, Yong-Ho Jeon
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Publication number: 20170200802Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.Type: ApplicationFiled: January 9, 2017Publication date: July 13, 2017Inventors: Sungwoo MYUNG, GeumJung SEONG, Jisoo OH, JinWook LEE, Dohyoung KIM, Yong-Ho JEON
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Publication number: 20160240630Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.Type: ApplicationFiled: January 6, 2016Publication date: August 18, 2016Inventors: GeumJung Seong, JinWook Lee, Dohyoung Kim, Sungwoo Myung, Jisoo Oh, Yong-Ho Jeon
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Patent number: 6498421Abstract: An ultrasonic suture device is provided for drilling arc shaped holes through hard materials, such as metals, glass, or bone. The ultrasonic suture device includes a transducer, horn and probe. The probe is constructed of three sections including a stem section, extension section and arc section. The stem section extends along the longitudinal axis of the ultrasonic suture device, while the arc section is constructed in the shape of an arc of a circle and is positioned concentrically with the stem's axis. At the distal extremity of the probe is a tip constructed for drilling into hard materials.Type: GrantFiled: June 15, 2001Date of Patent: December 24, 2002Assignee: Amega Lab, L.L.C.Inventors: Jisoo Oh, Ben Hur
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Publication number: 20020193798Abstract: An ultrasonic suture device is provided for drilling arc shaped holes through hard materials, such as metals, glass, or bone. The ultrasonic suture device includes a transducer, horn and probe. The probe is constructed of three sections including a stem section, extension section and arc section. The stem section extends along the longitudinal axis of the ultrasonic suture device, while the arc section is constructed in the shape of an arc of a circle and is positioned concentrically with the stem's axis. At the distal extremity of the probe is a tip constructed for drilling into hard materials.Type: ApplicationFiled: June 15, 2001Publication date: December 19, 2002Inventors: Jisoo Oh, Ben Hur