Patents by Inventor Jisoo Oh

Jisoo Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10522401
    Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungwoo Myung, GeumJung Seong, Jisoo Oh, JinWook Lee, Dohyoung Kim, Yong-Ho Jeon
  • Publication number: 20190157147
    Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 23, 2019
    Inventors: Sungwoo MYUNG, GeumJung SEONG, Jisoo OH, JinWook LEE, Dohyoung KIM, Yong-Ho JEON
  • Patent number: 10186457
    Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungwoo Myung, GeumJung Seong, Jisoo Oh, JinWook Lee, Dohyoung Kim, Yong-Ho Jeon
  • Patent number: 10043889
    Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: GeumJung Seong, JinWook Lee, Dohyoung Kim, Sungwoo Myung, Jisoo Oh, Yong-Ho Jeon
  • Publication number: 20180061958
    Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.
    Type: Application
    Filed: October 26, 2017
    Publication date: March 1, 2018
    Inventors: Sungwoo MYUNG, GeumJung SEONG, Jisoo OH, JinWook LEE, Dohyoung KIM, Yong-Ho JEON
  • Publication number: 20180033867
    Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.
    Type: Application
    Filed: October 3, 2017
    Publication date: February 1, 2018
    Inventors: GeumJung SEONG, JinWook LEE, Dohyoung KIM, Sungwoo MYUNG, Jisoo OH, Yong-Ho JEON
  • Patent number: 9806168
    Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: GeumJung Seong, JinWook Lee, Dohyoung Kim, Sungwoo Myung, Jisoo Oh, Yong-Ho Jeon
  • Patent number: 9806166
    Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungwoo Myung, GeumJung Seong, Jisoo Oh, JinWook Lee, Dohyoung Kim, Yong-Ho Jeon
  • Publication number: 20170200802
    Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 13, 2017
    Inventors: Sungwoo MYUNG, GeumJung SEONG, Jisoo OH, JinWook LEE, Dohyoung KIM, Yong-Ho JEON
  • Publication number: 20160240630
    Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.
    Type: Application
    Filed: January 6, 2016
    Publication date: August 18, 2016
    Inventors: GeumJung Seong, JinWook Lee, Dohyoung Kim, Sungwoo Myung, Jisoo Oh, Yong-Ho Jeon
  • Patent number: 6498421
    Abstract: An ultrasonic suture device is provided for drilling arc shaped holes through hard materials, such as metals, glass, or bone. The ultrasonic suture device includes a transducer, horn and probe. The probe is constructed of three sections including a stem section, extension section and arc section. The stem section extends along the longitudinal axis of the ultrasonic suture device, while the arc section is constructed in the shape of an arc of a circle and is positioned concentrically with the stem's axis. At the distal extremity of the probe is a tip constructed for drilling into hard materials.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: December 24, 2002
    Assignee: Amega Lab, L.L.C.
    Inventors: Jisoo Oh, Ben Hur
  • Publication number: 20020193798
    Abstract: An ultrasonic suture device is provided for drilling arc shaped holes through hard materials, such as metals, glass, or bone. The ultrasonic suture device includes a transducer, horn and probe. The probe is constructed of three sections including a stem section, extension section and arc section. The stem section extends along the longitudinal axis of the ultrasonic suture device, while the arc section is constructed in the shape of an arc of a circle and is positioned concentrically with the stem's axis. At the distal extremity of the probe is a tip constructed for drilling into hard materials.
    Type: Application
    Filed: June 15, 2001
    Publication date: December 19, 2002
    Inventors: Jisoo Oh, Ben Hur