Patents by Inventor Ji-Su Yu
Ji-Su Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11916120Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.Type: GrantFiled: May 10, 2022Date of Patent: February 27, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Su Yu, Hyeon Gyu You, Seung Man Lim
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Patent number: 11850574Abstract: A catalyst for preparing a synthesis gas includes: a mesoporous Al2O3 support including mesopores having a pore size of about 1 nm to about 30 nm; metal nanoparticles supported in the mesopores of the mesoporous Al2O3 support wherein the metal nanoparticles have a particle size of less than or equal to about 20 nm; and a metal oxide coating layer including particles wherein the metal oxide coating layer is coated on the surface of the mesoporous Al2O3 support and includes mesopores having a pore size of about 2 nm to about 50 nm.Type: GrantFiled: April 4, 2022Date of Patent: December 26, 2023Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, Research & Business Foundation SUNGKYUNKWAN UNIVERSITYInventors: Kyung Soo Park, Haeun Jeong, Jin Woo Choung, Ji Su Yu, Jae Min Park, Jong Wook Bae
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Patent number: 11845666Abstract: Disclosed is a method for preparing a synthesis gas. The method may include performing a combined reforming reaction by injecting a reaction gas including water (H2O) and heat-treating it in the presence of the catalyst. The catalyst may include a mesoporous support including regularly distributed mesopores, metal nanoparticles supported on the support, and a metal oxide coating layer coated on a surface of the support.Type: GrantFiled: April 7, 2021Date of Patent: December 19, 2023Assignees: Hyundai Motor Company, Kia Corporation, Research & Business Foundation Sungkyunkwan UniversityInventors: Haeun Jeong, Jin Woo Choung, Jong Wook Bae, Kyung Soo Park, Ji Su Yu, Jaehyeon Kwon
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Publication number: 20230381752Abstract: The present disclosure relates to a ternary catalyst coated with a metal oxide, the ternary catalyst including: a ternary catalyst core including a hydrotalcite support and metal particles dispersed on the support; and a metal oxide shell formed on the ternary catalyst core.Type: ApplicationFiled: April 26, 2023Publication date: November 30, 2023Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Jong Wook BAE, Jae Min PARK, Ji Su YU
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Patent number: 11810920Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.Type: GrantFiled: September 21, 2020Date of Patent: November 7, 2023Inventors: Ji Su Yu, Jae-Ho Park, Sanghoon Baek, Hyeon Gyu You, Seung Young Lee, Seung Man Lim
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Publication number: 20230335492Abstract: According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source/drain region having the second conductivity type, on the first well; a first source/drain contact extending in a second direction and electrically connected to the first power rail, on the first source/drain region, a first connection wiring electrically connected to the first source/drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.Type: ApplicationFiled: January 12, 2023Publication date: October 19, 2023Inventors: Jung Ho Do, Ji Su Yu, Jae Ha Lee
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Patent number: 11764201Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.Type: GrantFiled: January 26, 2021Date of Patent: September 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Su Yu, Jae-Woo Seo, Sanghoon Baek, Hyeon Gyu You
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Patent number: 11701647Abstract: Disclosed are a catalyst for preparing a synthetic gas through dry reforming, a method preparing the catalyst, and a method using the catalyst for preparing the synthetic gas. The catalyst may include: a support including regularly distributed mesopores; metal nanoparticles supported on the support; and a metal oxide coating layer coated on a surface of the support.Type: GrantFiled: September 28, 2020Date of Patent: July 18, 2023Assignees: Hyundai Motor Company, Kia Motors Corporation, Research & Business Foundation Sunskyunkwan UniversityInventors: Haeun Jeong, Jin Woo Choung, Kyung Soo Park, Jaehyeon Kwon, Ji Su Yu, Jong Wook Bae
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Publication number: 20230056669Abstract: A catalyst for preparing a synthesis gas includes: a mesoporous Al2O3 support including mesopores having a pore size of about 1 nm to about 30 nm; metal nanoparticles supported in the mesopores of the mesoporous Al2O3 support wherein the metal nanoparticles have a particle size of less than or equal to about 20 nm; and a metal oxide coating layer including particles wherein the metal oxide coating layer is coated on the surface of the mesoporous Al2O3 support and includes mesopores having a pore size of about 2 nm to about 50 nm.Type: ApplicationFiled: April 4, 2022Publication date: February 23, 2023Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, Research & Business Foundation SUNGKYUNKWAN UNIVERSITYInventors: Kyung Soo Park, Haeun Jeong, Jin Woo Choung, Ji Su Yu, Jae Min Park, Jong Wook Bae
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Patent number: 11488948Abstract: A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.Type: GrantFiled: December 2, 2020Date of Patent: November 1, 2022Inventors: Hyeon Gyu You, Ji Su Yu, Jae-Ho Park
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Publication number: 20220271133Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Su YU, Hyeon Gyu YOU, Seung Man LIM
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Patent number: 11355604Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.Type: GrantFiled: April 24, 2020Date of Patent: June 7, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Su Yu, Hyeon Gyu You, Seung Man Lim
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Publication number: 20220115406Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: ApplicationFiled: December 24, 2021Publication date: April 14, 2022Inventors: Hyeon Gyu YOU, In Gyum KIM, Gi Young YANG, Ji Su YU, Jin Young LIM, Hak Chul JUNG
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Publication number: 20220089436Abstract: Disclosed is a method for preparing a synthesis gas. The method may include performing a combined reforming reaction by injecting a reaction gas including water (H2O) and heat-treating it in the presence of the catalyst. The catalyst may include a mesoporous support including regularly distributed mesopores, metal nanoparticles supported on the support, and a metal oxide coating layer coated on a surface of the support.Type: ApplicationFiled: April 7, 2021Publication date: March 24, 2022Inventors: Haeun Jeong, Jin Woo Choung, Jong Wook Bae, Kyung Soo Park, Ji Su Yu, Jaehyeon Kwon
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Patent number: 11244961Abstract: An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor, a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor and a fourth first-type transistor, a plurality of wiring layers which are disposed on the first and second standard cells and includes a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers.Type: GrantFiled: May 30, 2020Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeon Gyu You, In Gyum Kim, Gi Young Yang, Ji Su Yu, Jin Young Lim, Hak Chul Jung
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Publication number: 20220032281Abstract: Disclosed are a catalyst for preparing a synthetic gas through dry reforming, a method preparing the catalyst, and a method using the catalyst for preparing the synthetic gas. The catalyst may include: a support including regularly distributed mesopores; metal nanoparticles supported on the support; and a metal oxide coating layer coated on a surface of the support.Type: ApplicationFiled: September 28, 2020Publication date: February 3, 2022Inventors: Haeun Jeong, Jin Woo Choung, Kyung Soo Park, Jaehyeon Kwon, Ji Su Yu, Jong Wook Bae
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Publication number: 20210384222Abstract: An integrated circuit includes a first cell arranged in a first row extending in a first horizontal direction, a second cell arranged in a second row adjacent to the first row, and a third cell continuously arranged in the first row and the second row. The first cell and the second cell comprise respective portions of a first power line extending in the first horizontal direction, and the third cell includes a second power line electrically connected to the first power line and extending in the first horizontal direction in the first row.Type: ApplicationFiled: August 19, 2021Publication date: December 9, 2021Inventors: Jung-ho Do, Ji-su Yu, Hyeon-gyu You, Seung-young Lee, Jae-boong Lee
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Patent number: 11183497Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.Type: GrantFiled: August 5, 2019Date of Patent: November 23, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Boong Lee, Jae-Ho Park, Sang-Hoon Baek, Ji-Su Yu, Seung-Young Lee, Jong-Hoon Jung
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Patent number: 11152392Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.Type: GrantFiled: September 28, 2020Date of Patent: October 19, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-ho Do, Ji-Su Yu, Hyeon-gyu You, Seung-Young Lee, Jae-boong Lee, Jong-hoon Jung
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Publication number: 20210313310Abstract: An integrated circuit including a plurality of standard cells is provided. The integrated circuit includes a first standard cell group including at least two first standard cells, a second standard cell group adjacent to the first standard cell group in a first direction, the second standard cell group including at least one second standard cell, and a first insulating gate bordered by one side of at least one of the first standard cells and one side of the at least one second standard cell, wherein each of the first and second standard cells includes a p-type transistor (pFET) and an n-type transistor (nFET) which are integrated, wherein each of the first and second standard cells has first wiring lines of different designs, and wherein each of the first and second standard cells has the same or different placement of an active region according to the corresponding design.Type: ApplicationFiled: January 26, 2021Publication date: October 7, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Su YU, Jae-Woo SEO, Sanghoon BAEK, Hyeon Gyu YOU