Patents by Inventor Jitendra Gupta

Jitendra Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10878892
    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Publication number: 20200364391
    Abstract: A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Applicant: Synopsys, Inc.
    Inventors: Alexander John WAKEFIELD, Jitendra GUPTA, Vaibhav JAIN, Rahul JAIN, Shweta BANSAL
  • Patent number: 10768977
    Abstract: A framework is described for editing, assigning, controlling, and monitoring multiple bots within an enterprise network, including bots that perform natural language processing. In one implementation, a method includes: initializing a bot controller application instance; receiving, at the bot controller application instance, registration information from bot hosts; retrieving, from a web services gateway, configuration information for each of the of bot hosts; and using at least the retrieved registration information and configuration information for each of the bot hosts, displaying at a graphical user interface of the bot controller application instance a summary of the registered bot hosts and data relating to scripts executed by each of the bot hosts.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 8, 2020
    Assignee: FIRST AMERICAN FINANCIAL CORPORATION
    Inventors: Angshuman Paul, Sana Ullah Khan, Jitendra Gupta
  • Patent number: 10748583
    Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 18, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10734065
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Navin Agarwal, Shri Sagar Dwivedi, Jitendra Dasani, Fakhruddin Ali Bohra, Lalit Gupta, Daksheshkumar Maganbhai Malaviya
  • Patent number: 10699668
    Abstract: Embodiments of systems and methods for providing configurable video redirection in a data center are discussed. In an embodiment, an Information Handling System (IHS) may include a Baseband Management Controller (BMC); and a memory coupled to the BMC, the memory having program instructions stored thereon that, upon execution by the BMC, cause the BMC to: receive a request from a remote client, where the request follows a first protocol; select one of a plurality of redirection components available to the IHS to populate a framebuffer with video frames using a second protocol; retrieve the video frames from the framebuffer; and transmit a response to the remote client following the first protocol, where the response comprises the video frames.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: June 30, 2020
    Assignee: Dell Products, L.P.
    Inventors: Chitrak Gupta, Rama Rao Bisa, Rajeshkumar Ichchhubhai Patel, Sushma Basavarajaiah, Elie Antoun Jreij, Jitendra Kumar
  • Patent number: 10672459
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Arm Limited
    Inventors: Yicong Li, Andy Wangkun Chen, Sharryl Renee Dettmer, Lalit Gupta, Jitendra Dasani, Yeon Jun Park, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10622038
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Arm Limited
    Inventors: Lalit Gupta, Fakhruddin Ali Bohra, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Gaurav Rattan Singla
  • Publication number: 20200005836
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Lalit Gupta, Fakhruddin Ali Bohra, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Gaurav Rattan Singla
  • Publication number: 20190371025
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for navigation using visual inputs. One of the systems includes a mapping subsystem configured to, at each time step of a plurality of time steps, generate a characterization of an environment from an image of the environment at the time step, wherein the characterization comprises an environment map identifying locations in the environment having a particular characteristic, and wherein generating the characterization comprises, for each time step: obtaining the image of the environment at the time step, processing the image to generate a first initial characterization for the time step, obtaining a final characterization for a previous time step, processing the characterization for the previous time step to generate a second initial characterization for the time step, and combining the first initial characterization and the second initial characterization to generate a final characterization for the time step.
    Type: Application
    Filed: February 9, 2018
    Publication date: December 5, 2019
    Inventors: Rahul Sukthankar, Saurabh Gupta, James Christopher Davidson, Sergey Vladimir Levine, Jitendra Malik
  • Publication number: 20190325949
    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Patent number: 10425076
    Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: September 24, 2019
    Assignee: ARM Limited
    Inventors: Lalit Gupta, Vivek Nautiyal, Andy Wangkun Chen, Jitendra Dasani, Bo Zheng, Akshay Kumar, Vivek Asthana
  • Publication number: 20190244656
    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Yicong Li, Andy Wangkun Chen, Sharryl Renee Dettmer, Lalit Gupta, Jitendra Dasani, Yeon Jun Park, Shri Sagar Dwivedi, Fakhruddin Ali Bohra
  • Publication number: 20190237135
    Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: Arjunesh Namboothiri Madhavan, Akash Bangalore Srinivasa, Sujit Kumar Rout, Vikash, Gaurav Rattan Singla, Vivek Nautiyal, Shri Sagar Dwivedi, Jitendra Dasani, Lalit Gupta
  • Publication number: 20190198064
    Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Lalit Gupta, Jitendra Dasani, Vivek Nautiyal, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Publication number: 20140298281
    Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.
    Type: Application
    Filed: October 16, 2013
    Publication date: October 2, 2014
    Applicant: Atrenta, Inc.
    Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
  • Patent number: 8839171
    Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: September 16, 2014
    Assignee: Atrenta, Inc.
    Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
  • Patent number: 8782582
    Abstract: This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: July 15, 2014
    Assignee: Atrenta, Inc.
    Inventors: Jitendra Gupta, Ashima Dabare, Kshitiz Krishna, Sanjiv Mathur, Ravi Varadarajan
  • Patent number: 8745567
    Abstract: A logical congestion metric analysis engine predicts pre-placement routing congestion of integrated circuit designs. The engine uses a method employing new congestion-predicting metrics derived from structural register transfer level (RTL). The method compares multiple metrics to those stored in a knowledge base to predict routing congestion. The knowledge base contains routing results for multiple designs using the same technology. For each design the knowledge base holds pre-placement metric values and the corresponding post-placement and routing congestion results. A logical congestion debug tool allows users to visualize and fix congestion issues.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 3, 2014
    Assignee: Atrenta, Inc.
    Inventors: Ravi Varadrajan, Jitendra Gupta, Priyank Mittal, Tapeesh Gupta, Navneet Mohindru
  • Publication number: 20120010930
    Abstract: In various embodiments, a rewards program may provide users with rewards for transacting with a merchant. In various embodiments, the transactions are validated before a user is allowed to receive a reward. In various embodiments, a mobile device is used to validate a transaction. In various embodiments, a mobile device may store an indication of a user's progress towards earning a reward.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 12, 2012
    Inventors: Graham Langdon, Jitendra Gupta