Patents by Inventor Jitendra Gupta

Jitendra Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11748151
    Abstract: A framework is described for editing, assigning, controlling, and monitoring multiple bots within an enterprise network, including bots that perform natural language processing. In one implementation, a method includes: initializing a bot controller application instance; receiving, at the bot controller application instance, registration information from bot hosts; retrieving, from a web services gateway, configuration information for each of the of bot hosts; and using at least the retrieved registration information and configuration information for each of the bot hosts, displaying at a graphical user interface of the bot controller application instance a summary of the registered bot hosts and data relating to scripts executed by each of the bot hosts.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 5, 2023
    Assignee: FIRST AMERICAN FINANCIAL CORPORATION
    Inventors: Angshuman Paul, Sana Ullah Khan, Jitendra Gupta
  • Patent number: 11443087
    Abstract: A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 13, 2022
    Assignee: SYNOPSYS, INC.
    Inventors: Alexander John Wakefield, Jitendra Gupta, Vaibhav Jain, Rahul Jain, Shweta Bansal
  • Publication number: 20220032977
    Abstract: A distributed power system includes a communication device and a control device. The communication device is configured to be disposed onboard a first vehicle of a vehicle system that also includes at least a second vehicle. The communication device is configured to communicate a discover message. The control device is configured to be operatively connected to the communication device, and, responsive to the communication device receiving a discover reply message from a second vehicle, to generate a configure message for the communication device to transmit to the second vehicle based on an identifier of the second vehicle included in the discover reply message. The configure message includes instructions for the second vehicle to transition to a remote mode of operation in which remote control of tractive and braking efforts of the second vehicle is enabled.
    Type: Application
    Filed: July 19, 2021
    Publication date: February 3, 2022
    Inventor: Jitendra Gupta
  • Publication number: 20200364391
    Abstract: A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Applicant: Synopsys, Inc.
    Inventors: Alexander John WAKEFIELD, Jitendra GUPTA, Vaibhav JAIN, Rahul JAIN, Shweta BANSAL
  • Patent number: 10768977
    Abstract: A framework is described for editing, assigning, controlling, and monitoring multiple bots within an enterprise network, including bots that perform natural language processing. In one implementation, a method includes: initializing a bot controller application instance; receiving, at the bot controller application instance, registration information from bot hosts; retrieving, from a web services gateway, configuration information for each of the of bot hosts; and using at least the retrieved registration information and configuration information for each of the bot hosts, displaying at a graphical user interface of the bot controller application instance a summary of the registered bot hosts and data relating to scripts executed by each of the bot hosts.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 8, 2020
    Assignee: FIRST AMERICAN FINANCIAL CORPORATION
    Inventors: Angshuman Paul, Sana Ullah Khan, Jitendra Gupta
  • Publication number: 20140298281
    Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.
    Type: Application
    Filed: October 16, 2013
    Publication date: October 2, 2014
    Applicant: Atrenta, Inc.
    Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
  • Patent number: 8839171
    Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: September 16, 2014
    Assignee: Atrenta, Inc.
    Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
  • Patent number: 8782582
    Abstract: This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: July 15, 2014
    Assignee: Atrenta, Inc.
    Inventors: Jitendra Gupta, Ashima Dabare, Kshitiz Krishna, Sanjiv Mathur, Ravi Varadarajan
  • Patent number: 8745567
    Abstract: A logical congestion metric analysis engine predicts pre-placement routing congestion of integrated circuit designs. The engine uses a method employing new congestion-predicting metrics derived from structural register transfer level (RTL). The method compares multiple metrics to those stored in a knowledge base to predict routing congestion. The knowledge base contains routing results for multiple designs using the same technology. For each design the knowledge base holds pre-placement metric values and the corresponding post-placement and routing congestion results. A logical congestion debug tool allows users to visualize and fix congestion issues.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 3, 2014
    Assignee: Atrenta, Inc.
    Inventors: Ravi Varadrajan, Jitendra Gupta, Priyank Mittal, Tapeesh Gupta, Navneet Mohindru
  • Publication number: 20120010930
    Abstract: In various embodiments, a rewards program may provide users with rewards for transacting with a merchant. In various embodiments, the transactions are validated before a user is allowed to receive a reward. In various embodiments, a mobile device is used to validate a transaction. In various embodiments, a mobile device may store an indication of a user's progress towards earning a reward.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 12, 2012
    Inventors: Graham Langdon, Jitendra Gupta
  • Patent number: 7496687
    Abstract: A business platform can provide access to applications and provide for the integration of resources with other applications, including internal and external applications, services and systems. A portal framework included within the platform can render portals including graphical user interfaces for displaying and receiving content that can be used by various applications. A portal framework can provide an interface to various resources such that information received and displayed by the portal framework can be exchanged with internal and external resources using standards-based transport protocols, messaging systems, and document types. An integration framework can be invoked to exchange this information among applications and services. An integration framework can provide access to resources by integrating the resources with an application server. The portal framework and integration framework can be implemented on an application server which can support enterprise applications.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: February 24, 2009
    Assignee: BEA Systems, Inc.
    Inventors: Philip B. Griffin, Troy Hallock, Brad Posner, Patrick Osborne, Olivier Libouban, Manish Devgan, Ravi Rohra, Jitendra Gupta, Somenath Sengupta, Hung T. Ma, Chengjiang Lin
  • Patent number: 7426548
    Abstract: A business platform can provide access to applications and provide for the integration of resources with other applications, including internal and external applications, services and systems. A portal framework included within the platform can render portals including graphical user interfaces for displaying and receiving content that can be used by various applications. A portal framework can provide an interface to various resources such that information received and displayed by the portal framework can be exchanged with internal and external resources using standards-based transport protocols, messaging systems, and document types. An integration framework can be invoked to exchange this information among applications and services. An integration framework can provide access to resources by integrating the resources with an application server. The portal framework and integration framework can be implemented on an application server which can support enterprise applications.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: September 16, 2008
    Assignee: BEA Systems, Inc.
    Inventors: Philip B. Griffin, Troy Hallock, Brad Posner, Patrick Osborne, Olivier Libouban, Manish Devgan, Ravi Rohra, Jitendra Gupta, Somenath Sengupta, Hung T. Ma, Chengjiang C. Lin
  • Publication number: 20080109491
    Abstract: A method and a system for evaluating the quality of a contribution made by a user in a distributed online community framework are disclosed. The quality of contribution is assessed by creating a reputation profile of the user across multiple online communities. The reputation profile contains a reputation score indicating the credibility of the user, user identification information, user participation statistics and user contribution information. Such reputation score is calculated based on the feedback provided by other users for the contribution made by the user. The system also allows maintaining and publishing a unique reputation profile across the distributed online communities. Maintaining the reputation profiles incentivizes users to contribute better quality content. This improves the overall quality of the community discourse.
    Type: Application
    Filed: November 3, 2007
    Publication date: May 8, 2008
    Applicant: SEZWHO INC.
    Inventor: Jitendra Gupta
  • Publication number: 20080109244
    Abstract: A method and a system for evaluating the quality of a contribution made by a user in a distributed online community framework are disclosed. The quality of contribution is assessed by assigning a reputation score to the user across multiple online communities. The reputation scores of users are assigned on the basis of contributions of users and ratings received from other users for the contribution. The method provides for users to rate each other across multiple communities. The invention further discloses a method and system for maintaining reputation profiles of users of online communities. The system also allows maintaining a unique reputation profile across the distributed online communities. Maintaining the reputation profiles incentivizes users to contribute better quality content. This improves the overall quality of the community discourse.
    Type: Application
    Filed: November 3, 2007
    Publication date: May 8, 2008
    Applicant: SEZWHO INC.
    Inventor: Jitendra Gupta
  • Publication number: 20080109245
    Abstract: A method and system evaluate the quality of a contribution in a particular domain made by a user of an online community. The quality of a contribution in a particular domain is assessed by assigning domain specific reputation score to the users of the online community. A domain specific reputation score is assigned to the user on the basis of ratings received from other users for the contribution as well as the relevance of the contribution with reference to the particular domain. Included are a method and system for determining reputation of a first user with respect to a second user. Reputation of the first user with respect to the second user is determined by assigning a second viewer specific reputation score to the first user. Attributes of the second user and quality of contribution made by the first user are determining factor for the second viewer specific reputation score.
    Type: Application
    Filed: November 3, 2007
    Publication date: May 8, 2008
    Applicant: SEZWHO INC.
    Inventor: Jitendra Gupta
  • Publication number: 20070214271
    Abstract: A business platform can provide access to applications and provide for the integration of resources with other applications, including internal and external applications, services and systems. A portal framework included within the platform can render portals including graphical user interfaces for displaying and receiving content that can be used by various applications. A portal framework can provide an interface to various resources such that information received and displayed by the portal framework can be exchanged with internal and external resources using standards-based transport protocols, messaging systems, and document types. An integration framework can be invoked to exchange this information among applications and services. An integration framework can provide access to resources by integrating the resources with an application server. The portal framework and integration framework can be implemented on an application server which can support enterprise applications.
    Type: Application
    Filed: May 15, 2007
    Publication date: September 13, 2007
    Applicant: BEA SYSTEMS, INC.
    Inventors: Philip Griffin, Troy Hallock, Brad Posner, Patrick Osborne, Olivier Libouban, Manish Devgan, Ravi Rohra, Jitendra Gupta, Somenath Sengupta, Hung Ma, Chengjiang Lin
  • Patent number: 6969745
    Abstract: A thermoplastic composition comprising, 1 to 30 weight percent of a cycloaliphatic polyester; and greater than or equal to 40 weight percent of a polyorganosiloxane/polycarbonate block copolymer.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 29, 2005
    Assignee: General Electric Company
    Inventors: Ajay Taraiya, Jitendra Gupta
  • Publication number: 20050137310
    Abstract: Polymer nanocomposites comprising an untreated phyllosilicate, a delaminating agent, a swelling agent, and a polyorganosiloxane-polycarbonate copolymer are disclosed. The polymer nanocomposites are valuable for producing articles having a combination of improved performance characteristics, such as tensile modulus, low temperature ductility, and melt volume rate.
    Type: Application
    Filed: December 19, 2003
    Publication date: June 23, 2005
    Inventors: Deval Gupta, Ajay Taraiya, Sumanda Bandyopadhyay, Sanjay Charati, A. Purushotham, Jitendra Gupta
  • Patent number: 6825266
    Abstract: A thermoplastic polymer molding composition useful for producing an article, where the molding composition comprises a polyorganosiloxane-polycarbonate block copolymer and a flow modifier; wherein the flow modifier is at least one selected from the group consisting of a polyalkylene glycol, a low weight average molecular weight polycarbonate polymer, or mixtures thereof; and further wherein the flow modifier reduces surface imperfections when molded into the article.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: November 30, 2004
    Assignee: General Electric Company
    Inventors: Ajay Kumar Taraiya, Jitendra Gupta, Gautam Chatterjee, Bala Ambravaneswaran
  • Publication number: 20040127635
    Abstract: A thermoplastic polymer molding composition useful for producing an article, where the molding composition comprises a polyorganosiloxane-polycarbonate block copolymer and a flow modifier; wherein the flow modifier is at least one selected from the group consisting of a polyalkylene glycol, a low weight average molecular weight polycarbonate polymer, or mixtures thereof; and further wherein the flow modifier reduces surface imperfections when molded into the article.
    Type: Application
    Filed: December 30, 2002
    Publication date: July 1, 2004
    Inventors: Ajay Kumar Taraiya, Jitendra Gupta, Gautam Chatterjee, Bala Ambravaneswaran