Patents by Inventor Jitendra Rayala

Jitendra Rayala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8279977
    Abstract: A signal decoder, a method of detecting an RF signal at a MIMO receiver and a MIMO receiver are disclosed herein. In one embodiment, the signal decoder includes: (1) a tree pruner configured to reduce a number of nodes of an MLD tree to expand based on modulation properties of the transmitted radio signals and SE enumeration of at least a portion of the MLD tree and (2) a vector sorter configured to sort multiple rows of child nodes of the MLD tree in parallel.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 2, 2012
    Assignee: Verisilicon
    Inventor: Jitendra Rayala
  • Publication number: 20120147945
    Abstract: A signal decoder, a method of detecting an RF signal at a MIMO receiver and a MIMO receiver are disclosed herein. In on embodiment, the signal decoder includes: (1) a tree pruner configured to reduce a number of nodes of an MLD tree to expand based on modulation properties of the transmitted radio signals and SE enumeration of at least a portion of the MLD tree and (2) a vector sorter configured to sort multiple rows of child nodes of the MLD tree in parallel.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Applicant: VeriSilicon
    Inventor: Jitendra Rayala
  • Patent number: 7574468
    Abstract: A distributed arithmetic multiply/accumulate (MAC) unit for computing inverse discrete cosine transformations (IDCTs). In one embodiment, the distributed arithmetic MAC unit includes: (1) a first pipeline stage configured to perform dot products on received sequential input data and (2) a second pipeline stage coupled to the first pipeline stage and configured to compute additions and subtractions of the dot products to yield sequential output data.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: August 11, 2009
    Assignee: VeriSilicon Holdings (Cayman Islands) Co. Ltd.
    Inventor: Jitendra Rayala
  • Patent number: 7386120
    Abstract: Method and apparatus for canceling an echo path by locating an active region thereof for subsequent application of a filter thereto. A plurality of far-end signals RIN(n) and a corresponding plurality of near-end signals SIN(n) are acquired. Correlation within the far-end and near-end signals RIN(n) and SIN(n) is removed and gain control applied to bring the corresponding ones of the far-end and near-end signals RIN(n) and SIN(n) to a uniform level. The plurality of far-end and near-end signals RIN(n) and SIN(n) are then stored in respective data blocks. The stored data blocks are subsequently processed together to determine a set of coefficients for a bank of adaptive filters. An energy estimate is computed for each one of the bank of adaptive filters and the location of the active region of the echo determined from the energy estimates.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: June 10, 2008
    Assignee: LSI Corporation
    Inventor: Jitendra Rayala