Patents by Inventor Jitesh Jain

Jitesh Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Computationally efficient modeling and simulation of large scale systems
    Patent number: 8745563
    Abstract: A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: June 3, 2014
    Assignee: Purdue Research Foundation
    Inventors: Jitesh Jain, Stephen F Cauley, Hong Li, Cheng-Kok Koh, Vankataramanan Balakrishnan
  • Computationally efficient modeling and simulation of large scale systems
    Patent number: 8336014
    Abstract: A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X?1 and at least one other matrix, with first equation including X?1Y, X?1A, and X?1P, and the second equation including X?1A and X?1P.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: December 18, 2012
    Assignee: Purdue Research Foundation
    Inventors: Jitesh Jain, Stephen F. Cauley, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan
  • Computationally efficient modeling and simulation of large scale systems
    Patent number: 7774725
    Abstract: A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X1 and at least one other matrix, with first equation including X1Y, X1A, and X1P, and the second equation including X1A and X1P.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: August 10, 2010
    Assignee: Purdue Research Foundation
    Inventors: Jitesh Jain, Stephen F. Cauley, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan