Patents by Inventor Jiun-cheng Hsieh

Jiun-cheng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8854050
    Abstract: A detection method of low frequency handshaking signal is described. The method includes the following steps of: (a) performing first impedance calibration when host device is activated for sending a first low frequency signal based on the first impedance calibration and performing a second impedance calibration when a controlled device is activated for sending a second low frequency signal based on the second impedance calibration; (b) transmitting a first high frequency training signal from the host device to the second receiver of the controlled device when the first low frequency signal and the second low frequency signal are in a predetermined condition; and (c) transmitting a second high frequency training signal from the controlled device to the first receiver of the host device wherein the frequency of the first low frequency signal and the second low frequency signal is smaller than the frequency of the first high frequency training signal and the second high frequency training signal.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: October 7, 2014
    Assignee: Genesys Logic, Inc.
    Inventor: Jiun-Cheng Hsieh
  • Patent number: 8553753
    Abstract: A clock-synchronized method for universal serial bus (USB) is described. The method includes the following steps of: (a) a transmitter sends a periodic signal to a host unit during a first time interval; (b) the host unit transmits a first equalization training sequence signal to a receiver during a second time interval to train the receiver and the transmitter continuously sends the periodic signal to the host unit; (c) a clock and data recovery device extracts the first equalization training sequence signal during the second time interval to generate a extracted clock signal and a data signal; and (d) the transmitter sends a second equalization training sequence signal to the host unit based on the extracted clock signal during the third time interval to train the host unit and the receiver and the transmitter commonly utilize the extracted clock signal as a reference clock.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: October 8, 2013
    Assignee: Genesys Logic, Inc.
    Inventors: Jiun-cheng Hsieh, Ying-chen Lin
  • Publication number: 20120119756
    Abstract: A detection method of low frequency handshaking signal is described. The method includes the following steps of: (a) performing first impedance calibration when host device is activated for sending a first low frequency signal based on the first impedance calibration and performing a second impedance calibration when a controlled device is activated for sending a second low frequency signal based on the second impedance calibration; (b) transmitting a first high frequency training signal from the host device to the second receiver of the controlled device when the first low frequency signal and the second low frequency signal are in a predetermined condition; and (c) transmitting a second high frequency training signal from the controlled device to the first receiver of the host device wherein the frequency of the first low frequency signal and the second low frequency signal is smaller than the frequency of the first high frequency training signal and the second high frequency training signal.
    Type: Application
    Filed: February 22, 2011
    Publication date: May 17, 2012
    Applicant: GENESYS LOGIC, INC.
    Inventor: Jiun-Cheng Hsieh
  • Publication number: 20120020404
    Abstract: A clock-synchronized method for universal serial bus (USB) is described. The method includes the following steps of: (a) a transmitter sends a periodic signal to a host unit during a first time interval; (b) the host unit transmits a first equalization training sequence signal to a receiver during a second time interval to train the receiver and the transmitter continuously sends the periodic signal to the host unit; (c) a clock and data recovery device extracts the first equalization training sequence signal during the second time interval to generate a extracted clock signal and a data signal; and (d) the transmitter sends a second equalization training sequence signal to the host unit based on the extracted clock signal during the third time interval to train the host unit and the receiver and the transmitter commonly utilize the extracted clock signal as a reference clock.
    Type: Application
    Filed: August 10, 2010
    Publication date: January 26, 2012
    Applicant: GENESYS LOGIC, INC.
    Inventors: Jiun-cheng Hsieh, Ying-chen Lin