Abstract: A system is provided that facilitates placing repeating flip-flop stations on signal lines within an integrated circuit. The system operates by first receiving a layout that includes multiple functional blocks, and a netlist that specifies interconnections for signals between these functional blocks. The system determines a transit time for a signal interconnecting the functional blocks. If this transit time exceeds an allowed time, the system divides the interconnection into two or more sections, wherein the transit times on the sections are each less than the allowed time. The system then places a repeating flip-flop station within a channel on the integrated circuit in a position that allows the transit time on these sections to be met. Next, the system routes the signal from the originating functional block through a flip-flop located at the repeating flip-flop station to a receiver at the destination functional block.

Abstract: A system is provided that facilitates placing repeating flip-flop stations on signal lines within an integrated circuit. The system operates by first receiving a layout that includes multiple functional blocks, and a netlist that specifies interconnections for signals between these functional blocks. The system determines a transit time for a signal interconnecting the functional blocks. If this transit time exceeds an allowed time, the system divides the interconnection into two or more sections, wherein the transit times on the sections are each less than the allowed time. The system then places a repeating flip-flop station within a channel on the integrated circuit in a position that allows the transit time on these sections to be met. Next, the system routes the signal from the originating functional block through a flip-flop located at the repeating flip-flop station to a receiver at the destination functional block.

Abstract: One embodiment of the present invention provides a system that facilitates routing integrated circuit traces to reduce inductive noise coupling. Upon receiving an integrated circuit layout, the system routes traces between circuit elements of the integrated circuit through multiple layers of the integrated circuit layout. In doing so, the system groups traces together within each layer and separates each group from adjacent groups in the same layer using a shield trace. The system also routes a nearby shield trace on a nearby layer so that the nearby shield trace runs parallel to and is substantially centered on a group of traces within the layer. In this way, the nearby shield trace also provides inductive shielding for the group of traces.