Patents by Inventor Jiun-Hong Lai

Jiun-Hong Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7588946
    Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: September 15, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Tsung Tso, Jiun-Hong Lai, Mei-Jen Wu, Li Te Hsu, Pin Chia Su, Po-Zen Chen
  • Publication number: 20070020777
    Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
    Type: Application
    Filed: July 25, 2005
    Publication date: January 25, 2007
    Inventors: Chia-Tsung Tso, Jiun-Hong Lai, Mei-Jen Wu, Li Hsu, Pin Su, Po-Zen Chen