Abstract: A method for evaluating capacitor weighting of an analog-to-digital (ADC) is provided. An equivalent weighting value of each composed capacitor in each sub-capacitor-array may be obtained by adding the switch device to the ADC which enables each sub-capacitor-array in a digital-to-analog (DAC) to be measured by each other. The ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and successive approximation result of each input signal.

Abstract: A method for evaluating capacitor weighting of an analog-to-digital (ADC) is provided. An equivalent weighting value of each composed capacitor in each sub-capacitor-array may be obtained by adding the switch device to the ADC which enables each sub-capacitor-array in a digital-to-analog (DAC) to be measured by each other. The ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and successive approximation result of each input signal.

Abstract: A method and an apparatus for evaluating weighting of elements of a DAC and a SAR ADC using the same are provided. An equivalent weighting of each composed element is obtained by adding a reference element with a reference weighting, an auxiliary DAC, and a search circuit into the SAR ADC, and the equivalent weighting is represented by the reference weighting. The SAR ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and the successive approximation result of each input signal. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.

Abstract: A successive approximation register analog to digital converter (SAR ADC) and a method of linearity calibration therein are provided. Each composed element Ei in a part of the composed elements includes a main constructed element Ei0 and wi sub constructed element Ei1, Ei2, . . . , Eiwi. The SAR ADC selects a part of the sub constructed elements Ei1, Ei2, . . . , Eiwi and make them non-functional when a missing decision level is caused by the composed element Ei. An overlap cancellation to the obtained missing code numbers is performed, compensation coefficients are updated according to the missing code numbers after the overlap cancellation, and a compensation to the corresponding digital value is performed according to the compensation coefficients. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.

Abstract: A successive approximation register analog to digital converter (SAR ADC) and a method of linearity calibration therein are provided. Each composed element Ei in a part of the composed elements includes a main constructed element Ei0 and wi sub constructed element Ei1, Ei2, . . . , Eiwi. The SAR ADC selects a part of the sub constructed elements Ei1, Ei2, . . . , Eiwi and make them non-functional when a missing decision level is caused by the composed element Ei. An overlap cancellation to the obtained missing code numbers is performed, compensation coefficients are updated according to the missing code numbers after the overlap cancellation, and a compensation to the corresponding digital value is performed according to the compensation coefficients. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.

Abstract: A method and an apparatus for evaluating weighting of elements of a DAC and a SAR ADC using the same are provided. An equivalent weighting of each composed element is obtained by adding a reference element with a reference weighting, an auxiliary DAC, and a search circuit into the SAR ADC, and the equivalent weighting is represented by the reference weighting. The SAR ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and the successive approximation result of each input signal. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.

Abstract: A non-invasive array-based hemodynamic monitoring system on chip is disclosed. The non-invasive array-based hemodynamic monitoring system on chip comprises a CMOS MEMS pressure sensor array, a readout circuit, and a signal control system. The CMOS MEMS pressure sensor array is configured to sense a pulse wave of a blood vessel. The readout circuit is coupled with each of the CMOS compatible MEMS pressure sensors and is configured to read the pulse wave and transformed the pulse wave into a voltage signal. The signal control system is coupled with each of the readout circuit, and is configured to estimate a wave velocity according to the voltage signal.

Abstract: Provided are a generation device and the like for generating a new vector whose volume can be reduced rapidly when an output pattern derived from a decompressor of a logic circuit under test includes an unspecified bit in relation to the logic circuit under test. The output pattern includes unspecified bits. In step SS1, classification unit classifies the unspecified bits and determines if an unspecified bit is an implied bit or not. The implied bit is an unspecified bit if its value is a logic value determined as logic value 0 or 1 relating to logic bits in the initial vector and according to a predetermined condition (such as compressibility) among bits in the initial vector derived from the upstream logic circuit 1. In step SS1, the unspecified bits which are not implied bits are classified as free bits. The classification unit classifies free bit sets in step SS2, and further classifies free bits to identify compatible free bit sets.

Abstract: An apparatus for testing a driving circuit for a display is disclosed. The apparatus includes a selecting circuit, a reference voltage generator and an analog-to-digital converter (ADC). The selecting circuit includes many input terminals and an output terminal. The input terminals are respectively coupled to many output pins of the driving circuit, while the selecting circuit is used for selecting one of the output pins to electrically connect the output terminal of the selecting circuit. The reference voltage generator is coupled to at least one of the output pins for generating a reference voltage. The ADC is coupled to the output terminal of the selecting circuit for outputting a digital value based on a difference between an output voltage outputted from the output terminal of the selecting circuit and the reference voltage produced by the reference voltage generator.

Abstract: An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.

Abstract: An apparatus for testing a driving circuit for a display is disclosed. The apparatus includes a selecting circuit, a reference voltage generator and an analog-to-digital converter (ADC). The selecting circuit includes many input terminals and an output terminal. The input terminals are respectively coupled to many output pins of the driving circuit, while the selecting circuit is used for selecting one of the output pins to electrically connect the output terminal of the selecting circuit. The reference voltage generator is coupled to at least one of the output pins for generating a reference voltage. The ADC is coupled to the output terminal of the selecting circuit for outputting a digital value based on a difference between an output voltage outputted from the output terminal of the selecting circuit and the reference voltage produced by the reference voltage generator.

Abstract: An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.