Patents by Inventor Jiun-Lei Yu
Jiun-Lei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014176Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) semiconductor structure for wide-bandgap semiconductor devices in which the wide-bandgap semiconductor devices are split amongst a first IC die and a second IC die. The first IC die includes a first substrate and a first semiconductor device. The first substrate includes a first wide-bandgap material, and the first semiconductor device overlies the first substrate and is formed in part by the first wide-bandgap material. The second IC die overlies the first IC die and is bonded to the first IC die by a bond structure between the first and second IC dies. Further, the second IC die includes a second substrate and a second semiconductor device. The second substrate includes a second wide-bandgap material, and the second semiconductor device underlies the second substrate and is formed in part by the second wide-bandgap material.Type: ApplicationFiled: January 4, 2023Publication date: January 11, 2024Inventors: Ting-Fu Chang, Jiun-Lei Yu, Man-Ho Kwan, Chun-Lin Tsai
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Publication number: 20230369245Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.Type: ApplicationFiled: July 20, 2023Publication date: November 16, 2023Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
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Publication number: 20230343693Abstract: A semiconductor device includes a first semiconductor structure including a first high electron mobility transistor (HEMT) device, wherein the first HEMT device includes a first gate, a first source, and a first drain; and a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second HEMT device and a third HEMT device, wherein the second HEMT device includes a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device includes a third gate, a third source, and a third drain that is electrically connected to the first gate.Type: ApplicationFiled: August 1, 2022Publication date: October 26, 2023Inventors: Haw-Yun Wu, Chen-Bau Wu, Jiun-Lei Yu, Chun-Lin Tsai
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Patent number: 11798899Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.Type: GrantFiled: August 2, 2021Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
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Publication number: 20230253455Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Yu-Syuan LIN, Jiun-Lei YU, Ming-Cheng LIN, Chun Lin TSAI
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Patent number: 11631741Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: GrantFiled: July 27, 2020Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Syuan Lin, Jiun-Lei Yu, Ming-Cheng Lin, Chun Lin Tsai
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Publication number: 20220375875Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.Type: ApplicationFiled: August 2, 2021Publication date: November 24, 2022Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
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Patent number: 11222968Abstract: The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.Type: GrantFiled: December 30, 2019Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po-Chih Chen, Jiun-Lei Yu, Yao-Chung Chang, Chun-Lin Tsai
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Publication number: 20200357910Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Yu-Syuan LIN, Jiun-Lei YU, Ming-Cheng LIN, Chun Lin TSAI
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Patent number: 10727329Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: GrantFiled: December 13, 2018Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Syuan Lin, Jiun-Lei Yu, Ming-Cheng Lin, Chun Lin Tsai
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Publication number: 20200144408Abstract: The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.Type: ApplicationFiled: December 30, 2019Publication date: May 7, 2020Inventors: PO-CHIH CHEN, JIUN-LEI YU, YAO-CHUNG CHANG, CHUN-LIN TSAI
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Patent number: 10522671Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.Type: GrantFiled: August 27, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po-Chih Chen, Jiun-Lei Yu, Yao-Chung Chang, Chun-Lin Tsai
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Publication number: 20190131442Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: ApplicationFiled: December 13, 2018Publication date: May 2, 2019Inventors: Yu-Syuan LIN, Jiun-Lei YU, Ming-Cheng LIN, Chun Lin TSAI
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Patent number: 10170613Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: GrantFiled: July 31, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Syuan Lin, Jiun-Lei Yu, Ming-Cheng Lin, Chun Lin Tsai
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Publication number: 20180374945Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.Type: ApplicationFiled: August 27, 2018Publication date: December 27, 2018Inventors: PO-CHIH CHEN, JIUN-LEI YU, YAO-CHUNG CHANG, CHUN-LIN TSAI
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Patent number: 10062776Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.Type: GrantFiled: February 5, 2016Date of Patent: August 28, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po-Chih Chen, Jiun-Lei Yu, Yao-Chung Chang, Chun-Lin Tsai
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Publication number: 20180026029Abstract: The present disclosure relates to an electrostatic discharge (ESD) protection circuit integrated with a gallium nitride (GaN) based transistor and configured to clamp a gate input voltage of the gallium nitride (GaN) based transistor during an ESD surge event, and associated methods. In some embodiments, the ESD protection circuit includes a first ESD protection stage and a second ESD protection stage connected between a gate terminal and a source terminal of the GaN based transistor. The first ESD protection stage includes a first plurality of GaN based gate-to-source shorted transistors connected in series and further connected to a first terminal of a first resistor. The second ESD protection stage is connected to the first ESD protection stage in parallel. The second ESD protection stage comprises a first GaN based shunt transistor having a gate terminal connected to the first terminal of the first resistor.Type: ApplicationFiled: July 21, 2016Publication date: January 25, 2018Inventors: Yu-Syuan Lin, Ming-Cheng Lin, King-Yuen Wong, Jiun-Lei Yu, Chun Lin Tsai
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Publication number: 20170358671Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: ApplicationFiled: July 31, 2017Publication date: December 14, 2017Inventors: Yu-Syuan LIN, Jiun-Lei YU, Ming-Cheng LIN, Chun Lin TSAI
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Publication number: 20170229568Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.Type: ApplicationFiled: February 5, 2016Publication date: August 10, 2017Inventors: PO-CHIH CHEN, JIUN-LEI YU, YAO-CHUNG CHANG, CHUN-LIN TSAI
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Publication number: 20170222031Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.Type: ApplicationFiled: February 3, 2016Publication date: August 3, 2017Inventors: YU-SYUAN LIN, JIUN-LEI YU, MING-CHENG LIN, CHUN LIN TSAI