Patents by Inventor Jiun Nan Chen

Jiun Nan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7884412
    Abstract: A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: February 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shieh Feng Huang, Jiun Nan Chen, Lien Yo Tsai
  • Patent number: 7148098
    Abstract: A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: December 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shieh Feng Huang, Jiun Nan Chen, Lien Yo Tsai
  • Patent number: 6958249
    Abstract: A new method is provided for monitoring the effect of electron charging during the creation of a semiconductor device. The method of the invention makes use of electron trapping that occurs as a result of FN tunneling in a layer of interlayer oxide of an EEPROM device. The electron trapping is monitored under conditions of processing. After the electron trapping has occurred, the rate of discharge of the trapped electron charge is measured during Wafer Acceptance Testing (WAT).
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: October 25, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jiann-Tyng Tzeng, Yuh-Hwa Chang, Jiun-Nan Chen
  • Patent number: 6947196
    Abstract: A double substrate spatial light modulator with an enlarged tilt angle is achieved. The device comprises a mirror attached on one end to a hinge wherein the hinge is attached to support posts adjacent to the mirror and attached to an underlying glass substrate, a trench within the glass substrate adjacent to the support posts wherein the mirror tilts upward from the glass substrate and downward into the trench, and an overlying glass substrate. The trench provides an enlarged tilt angle of mirror motion. This improves optical performance of the mirror projector including contrast ratio and gray scale.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: September 20, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun Nan Chen, Yuh-Hwa Chang, Jiann Tyng Tzeng
  • Publication number: 20050157370
    Abstract: A deformable mirror device spatial light modulator employs a pair of substrates each having formed therein a deflection electrode. The pair of deflection electrodes is separated by a gap having positioned therein a deformable mirror which is registered with both of the pair of deflection electrodes. Appropriate magnitudes and polarities of voltages are applied to the pair of deflection electrodes and the deformable mirror such as to deflect the deformable mirror with enhanced deflection control.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 21, 2005
    Inventor: Jiun-Nan Chen
  • Publication number: 20040212868
    Abstract: A double substrate spatial light modulator with an enlarged tilt angle is achieved. The device comprises a mirror attached on one end to a hinge wherein the hinge is attached to support posts adjacent to the mirror and attached to an underlying glass substrate, a trench within the glass substrate adjacent to the support posts wherein the mirror tilts upward from the glass substrate and downward into the trench, and an overlying glass substrate. The trench provides an enlarged tilt angle of mirror motion. This improves optical performance of the mirror projector including contrast ratio and gray scale.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co.
    Inventors: Jiun Nan Chen, Yuh-Hwa Chang, Jiann Tyng Tzeng
  • Patent number: 6808985
    Abstract: A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming simulations on the prototype, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line by skipping certain Flash/EEPROM steps and then implanting the ROM code into the final ROM product. The method improves turn-around-time in the manufacturing line, and reduces cost to the customer. A method of doing business is also disclosed directed to providing ROM products to a customer without much redesign time and effort on the part of the customer.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: October 26, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuei-Ying Lee, Shao-Yu Chou, Jiun-Nan Chen, Yue-Der Chih, Sam Sheng-Deh Chu, Feng-Ming Kuo
  • Patent number: 6803283
    Abstract: A new method to form ROM devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. MOS gates are formed overlying the substrate. Ions are implanted into the substrate to form lightly doped drains for the MOS gates. A masking layer is used to offset the lightly doped drains from selective MOS gates to thereby form constant-OFF MOS gates. Spacers are next formed on the sidewalls of the MOS gates. Finally, ions are implanted into the substrate to form source and drain regions for the MOS gates to thereby complete the ROM devices in the manufacture of said integrated circuit device. The method may be extended to form ROM devices from Flash gates in a FlashROM process.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: October 12, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventor: Jiun-Nan Chen