Patents by Inventor Jiun Yi Wu

Jiun Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218020
    Abstract: A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Yu-Min Liang
  • Patent number: 12218021
    Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Jiun-Yi Wu, Hsin-Yu Pan, Tsung-Ding Wang, Yu-Min Liang, Wei-Yu Chen
  • Patent number: 12217976
    Abstract: A method of fabrication a package and a stencil structure are provided. The stencil structure includes a first carrier having a groove and stencil units placed in the groove of the first carrier. At least one of the stencil units is slidably disposed along sidewalls of another stencil unit. Each of the stencil units has openings.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu
  • Patent number: 12211779
    Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 12205879
    Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 12199080
    Abstract: A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 12193168
    Abstract: Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 12191251
    Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chien-Hsun Chen
  • Patent number: 12183682
    Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Chien-Hsun Lee, Chung-Shi Liu, Jiun-Yi Wu, Shou-Yi Wang, Tsung-Ding Wang
  • Patent number: 12183700
    Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Publication number: 20240427081
    Abstract: Optical devices and methods of manufacture are presented herein. In an embodiment, an optical device is provided that includes a first substrate, the first substrate including an optical device layer, and a semiconductor die, a first waveguide structure over the first substrate, the first waveguide structure including a first optical component surrounded by cladding material, wherein the first waveguide structure has a top surface, the top surface including a first portion at a first distance from the first substrate, a second portion at a second distance from the first substrate, and a transition portion between the first portion to the second portion, wherein the second distance is greater than the first distance, and a first reflective structure over the first portion and the transition portion, wherein a portion of the first reflective structure over the transition portion is a curved surface.
    Type: Application
    Filed: January 2, 2024
    Publication date: December 26, 2024
    Inventors: Chia-Ning Weng, Yu-Ming Chou, Shih Wei Liang, Nien-Fang Wu, Jiun Yi Wu, Chen-Hua Yu
  • Publication number: 20240427097
    Abstract: A photonic assembly includes: a composite die including a photonic integrated circuits (PIC) die and an electronic integrated circuits (EIC) die, the PIC die including waveguides and photonic devices therein, and the EIC die including semiconductor devices therein; and an optical connector unit including a first connector-side mirror reflector and a first transition edge coupler, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler.
    Type: Application
    Filed: November 17, 2023
    Publication date: December 26, 2024
    Inventors: Chen-Hua Yu, Chih-Wei Tseng, Hsing-Kuo Hsia, Jiun Yi Wu
  • Publication number: 20240427091
    Abstract: A photonic assembly includes: a composite die including a photonic integrated circuits (PIC) die and an electronic integrated circuits (EIC) die, the PIC die including waveguides and photonic devices therein, and the EIC die including semiconductor devices therein; an optical connector unit including a first connector-side mirror reflector and a first transition edge coupler and attached to a top surface of the composite die, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler; and a fiber array units assembly attached to a sidewall of the optical connector unit.
    Type: Application
    Filed: November 12, 2023
    Publication date: December 26, 2024
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Chih-Wei Tseng, Jiun Yi Wu, Szu-Wei Lu, Jui Lin Chao
  • Patent number: 12170267
    Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Publication number: 20240411093
    Abstract: An optical component is provided. The optical component includes a silicon-based body including a bottom wall, a first side wall, a second side wall, and a micro lens structure. The first side wall is located on a first side of the silicon-based body and perpendicular to the bottom wall. The second side wall is located on a second side of the silicon-based body opposite to the first side, and forms an acute angle with the bottom wall. The micro lens structure is formed on the first side wall. The optical component further includes a protection layer formed over the first side wall and the micro lens structure.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 12, 2024
    Inventors: Shih-Wei LIANG, Chen-Hua YU, Jiun-Yi WU, Nien-Fang WU
  • Patent number: 12165941
    Abstract: An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 12159822
    Abstract: A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Publication number: 20240395726
    Abstract: A semiconductor package and methods of forming the same are disclosed. In an embodiment, a package includes a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Publication number: 20240395683
    Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Publication number: 20240395685
    Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Jiun Yi Wu, Chen-Hua Yu