Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

Abstract: Polishing systems and methods for polishing a substrate are provided. The method includes polishing a substrate using a polishing pad and monitoring a thickness of the polishing pad. The monitoring of the thickness of the polishing pad is performed by detecting an eddy current generated from a conductor element below a bottom surface of the polishing pad. The method also includes replacing the polishing pad with a second polishing pad if the thickness of the polishing pad is smaller than a predetermined value.

Abstract: Polishing systems and methods for polishing a substrate are provided. The method includes polishing a substrate using a polishing pad and monitoring a thickness of the polishing pad. The monitoring of the thickness of the polishing pad is performed by detecting an eddy current generated from a conductor element below a bottom surface of the polishing pad. The method also includes replacing the polishing pad with a second polishing pad if the thickness of the polishing pad is smaller than a predetermined value.

Abstract: Polishing systems and methods for polishing a substrate are provided. The polishing system includes a polishing assembly having a platen and a polishing pad over the platen. The polishing system also includes a substrate carrying assembly configured to engage a substrate to the polishing pad. The polishing system further includes a thickness sensing assembly configured to monitor a thickness of the polishing pad.

Abstract: Polishing systems and methods for polishing a substrate are provided. The polishing system includes a polishing assembly having a platen and a polishing pad over the platen. The polishing system also includes a substrate carrying assembly configured to engage a substrate to the polishing pad. The polishing system further includes a thickness sensing assembly configured to monitor a thickness of the polishing pad.

Abstract: A method of chemical mechanical polishing of a metal damascene structure which includes an insulation layer having trenches on a wafer and a metal layer having a lower portion located in trenches of the insulation layer and an upper portion overlying the lower portion and the insulation layer is provided. The method comprises a first step of planarizing the upper portion of the metal layer and a second step of polishing the insulation layer and the lower portion of the metal layer. In the first step of planarizing the upper portion of the metal layer, the wafer and a polishing pad is urged at an applied pressure p and a relative velocity v in a contact mode between the wafer and the polishing pad to promote an increased metal removal rate. In the second, the insulation layer and the lower portion of the metal layer are polished in a steady-state mode to form individual metal lines in the trenches with minimal dishing of the metal lines and overpolishing of the insulation layer.

Abstract: A method of chemical mechanical polishing of a metal damascene structure which includes an insulation layer having trenches on a wafer and a metal layer having a lower portion located in trenches of the insulation layer and an upper portion overlying the lower portion and the insulation layer is provided. The method comprises a first step of planarizing the upper portion of the metal layer and a second step of polishing the insulation layer and the lower portion of the metal layer. In the first step of planarizing the upper portion of the metal layer, the wafer and a polishing pad is urged at an applied pressure p and a relative velocity v in a contact mode between the wafer and the polishing pad to promote an increased metal removal rate. In the second, the insulation layer and the lower portion of the metal layer are polished in a steady-state mode to form individual metal lines in the trenches with minimal dishing of the metal lines and overpolishing of the insulation layer.

Abstract: In the Chemical Mechanical Polishing (CMP) process employed for microelectronics manufacturing, three contact regimes between the wafer surface and the polishing pad may be proposed: direct contact, mixed or partial contact, and hydroplaning. However, an effective in situ method for characterizing the wafer/pad contact and a systematic way of relating contact conditions to the process parameters are still lacking. In this work, the interfacial friction force, measured by a load sensor on the wafer carrier, has been employed to characterize the contact conditions. Models that relate the friction coefficient to the applied pressure, relative velocity, and slurry viscosity are developed and verified by experiments. Additionally, a correlation between friction coefficient and the material removal rate (MR) is established and the effects of process parameters on the Preston constant are investigated.