Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.

Abstract: A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.

Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.

Abstract: Apparatus and methods are disclosed for managing power consumption of a graphics processing system. Specifically, the method adaptively adjusts the performance level of the graphics processing system based on scene information in each frame. A scene-aware power manager is configured to receive scene information and adaptively control performance of the GPU according to the received scene information. The power manager compares the early indicators of the current frame with the early indicators of a previous frame to determine a level of scene change and to assign a set of initial performance settings based on the determined level of scene change.

Abstract: The invention provides the image method and apparatus to increase the sharpness of a resized image. The image includes a plurality of pixels with an alpha value and an image data. The method detects the alpha value of neighboring first and second pixels. Weighting values of interpolated pixels between the first and second pixels are determined. The image data of the interpolated pixels are set to be identical to the image data of the first pixel when one of the first pixel or the second pixel is zero.

Abstract: The invention provides the image method and apparatus to increase the sharpness of a resized image. The image includes a plurality of pixels with an alpha value and an image data. The method detects the alpha value of neighboring first and second pixels. Weighting values of interpolated pixels between the first and second pixels are determined. The image data of the interpolated pixels are set to be identical to the image data of the first pixel when one of the first pixel or the second pixel is zero.

Abstract: A display-supporting frame includes: first rods, each of which has first and second side walls, one of the first side walls being formed with first hole units, one of the second side walls being formed with second hole units, each of the first hole units cooperating with an adjacent one of the second hole units to define a plane transverse to the first and second side walls such that each pair of the first and second hole units are respectively located at two sides of the plane; second rods, each of which is formed with a locking hole unit; and a plurality of fasteners for fastening the first rods to the second rods through extension of each of the fasteners through a selected one of the first hole units and the second hole units in a respective one of the first rods, and into the locking hole unit in a respective one of the second rods to engage the respective one of the second rods.

Abstract: A system for scaling a picture unit from a first video resolution format to a second video resolution format, the picture unit being encoded utilizing a specific encoding scheme, is disclosed. The system includes: a FIFO, for buffering an encoded bit stream of the PU; a decoding circuit, coupled to the FIFO, for receiving the encoded bit stream of the PU, and decoding the encoded bit stream to generate a plurality of pixel data; a scaling circuit, coupled to the decoding circuit and the FIFO, for controlling the decoding circuit to duplicate at least a pixel data according to a scaling factor of the first video resolution format to the second video resolution format; and a look-up table, coupled to the scaling circuit and the decoding circuit, containing a plurality of values corresponding to the pixel data.

Abstract: The present invention discloses a method to manufacture a self-aligned silicide layer on a substrate. A metal oxide semiconductor (MOS) device and a shallow trench are fabricated in the substrate. The device has a gate structure, spacers of the gate structured and doping regions. The shallow trench is refilled with silicon oxide material for isolation. A silicon layer is nonconformally deposited on the top surface of the gate structure, the spacers and the doping regions by using a physical vapor deposition (PVD) process, such as ion metal plasma (IMP) process. The IMP process, like a sputtering process, is to ionize a silicon material or a refractory-metal material to silicon ions or metal ions and the ions are biased to anisotropically deposit on the top surface of the substrate. A refractory metal layer is defined on the top surface of the silicon layer by the IMP technology.

Abstract: A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.

Abstract: A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds.