Abstract: A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.

Abstract: A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.

Abstract: A capacitor structure including a conductive layer and a dielectric layer is provided. The conductive layer includes a first pattern and a second pattern arranged alternatively with respect to each other. In addition, the dielectric layer is disposed between the first spiral pattern and the second spiral pattern. Since in the capacitor structure described in the present invention, the first pattern and the second pattern being used as electrodes are disposed in a spiral shape, the capacitance per unit area of the capacitor structure is increased.

Abstract: A capacitor structure including a conductive layer and a dielectric layer is provided. The conductive layer includes a first pattern and a second pattern arranged alternatively with respect to each other. In addition, the dielectric layer is disposed between the first spiral pattern and the second spiral pattern. Since in the capacitor structure described in the present invention, the first pattern and the second pattern being used as electrodes are disposed in a spiral shape, the capacitance per unit area of the capacitor structure is increased.

Abstract: An input/output (I/O) circuit with a high I/O voltage tolerance is provided for use in conjunction with an IC device that operates with two system voltages, such as 3.3 V and 5 V. The particular circuit configuration of this I/O circuit allows it to be fabricated using the Single Gate-Oxide technology instead of the Double Gate-Oxide technology, so that the manufacturing cost can be reduced as compared to the prior art. Moreover, this I/O circuit allows an output impedance lower than that of the prior art, allowing the signal transmission speed via this I/O circuit to be increased by about 30% as compared to the prior art. It can also help eliminate the problems of poor gate oxide reliability, PN junction inversion, and PMOS leakage that otherwise occur in the prior art. Furthermore, this I/O circuit can help eliminate the DC leakage current in the input-stage circuit, so that the power consumption can be reduced compared to the prior art.

Abstract: An input/output circuit with wide voltage tolerance is using a feedback circuit for increasing the voltage tolerance. A single gate oxide structure is fabricated instead of a dual gate oxide structure.