Patents by Inventor Jiunn-Hsien Lin

Jiunn-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12242738
    Abstract: A card reader and a controller thereof, and a method are provided. The card reader includes a storage device and the controller, wherein the controller is coupled to the storage device. The storage device is configured to store specific identification data of a specific memory device. The controller is configured to receive identification data of the external memory device plugged into the card reader, and determine whether the external memory device is the specific memory device according to the identification data and the specific identification data, to generate a determination result. More particularly, the controller may control whether to open permission of at least one function according to the determination result.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: March 4, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jiunn-Hung Shiau, Neng-Hsien Lin
  • Patent number: 12242744
    Abstract: A method of identifying the type of a memory card is provided for identifying the type of a secure digital (SD) card. The pin number of the SD card complies with an SD card specification formulated by the Secure Digital Association. The method includes the following steps: performing a legacy SD card initialization procedure on the SD card; and sequentially determining whether the SD card is an SD Express card, an Ultra High Speed type II (UHS-II) SD card, or a legacy SD card.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: March 4, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jiunn-Hung Shiau, Neng-Hsien Lin
  • Patent number: 12223373
    Abstract: An electronic device capable of accessing a memory card is provided. The electronic device includes a circuit board, a processing unit, a memory card slot, and a memory card access module. The processing unit is disposed on the circuit board. The memory card slot is disposed on the circuit board, allows the insertion of the memory card, and is coupled to the processing unit through a first signal line. The memory card access module is disposed on the circuit board for accessing the memory card. The memory card access module is coupled to the processing unit through a second signal line and coupled to the memory card slot through a third signal line and a fourth signal line. The first signal line, the second signal line, and the third signal line conform to the standard of a signal transmission interface.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: February 11, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jiunn-Hung Shiau, Neng-Hsien Lin
  • Patent number: 6197680
    Abstract: An improved method of forming a conductive line on a semiconductor substrate is described. A conductive layer is formed on the substrate. A patterned photoresist layer is formed on the conductive layer. A first etching step is performed on the conductive layer to define the conductive layer and to form a conductive line. A second etching step is performed on the conductive line to undercut the conductive line so as to make the conductive line have smaller bottom and to increase a distance between neighboring conductive lines. A third etching step is performed to remove residue generated on the substrate during the first and the second etching steps. A dielectric layer is formed to cover the conductive line. A planarization process is performed.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: March 6, 2001
    Assignee: United Semiconductor Corp.
    Inventors: Jiunn-Hsien Lin, Wen-Pin Kuo
  • Patent number: 5998286
    Abstract: The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: December 7, 1999
    Assignee: United Semiconductor Circuit Corp.
    Inventors: Shu-Jen Chen, Jacky Kuo, Jiunn-Hsien Lin, Chih-Ching Hsu
  • Patent number: 5960321
    Abstract: A method of forming a contact via includes forming a wiring, a first insulator layer, and a spin-on glass layer, respectively, over a semiconductor substrate. Fluorine ions are implanted into the spin-on glass layer. A second insulator layer is formed over the spin-on glass layer. The wiring is exposed by patterning the second insulator layer, the spin-on glass layer, and the first insulator layer, respectively.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: September 28, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Hsing Hsieh, Chin-Ching Hsu, Chen-Chih Tsai, Jiunn Hsien Lin
  • Patent number: 5924010
    Abstract: A method of fabricating salicide and self-aligned barrier simultaneously is disclosed. The initial steps include sputtering a metal stack (Ti--TiN--Ti) and forming a salicide layer by thermally reacting the metal stack and the wafer followed by a chemical etching which removes the unreacted portions of the metal stack. The portions of the metal stack on Si can react with Si to form a TiSi.sub.2 layer, thus forming TiSi.sub.2 --TiN--TiSi.sub.2. The TiSi.sub.2 layer over the TiN layer acts as a mask in the chemical etching and protects the TiN layer from been etched. The diffusion barrier layer is thus formed simultaneously within the fabricating of salicide.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: July 13, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Jen Chen, Jiunn-Hsien Lin, Chih-Ching Hsu
  • Patent number: 5731226
    Abstract: A method of manufacturing epitaxial titanium silicide in a metal silicide processing has a lower than usual processing temperature requirement, and is therefore suitable for use in the manufacturing of integrated circuits. The epitaxial titanium silicide so formed is made without a grain boundary and is thus capable of lowering the electrical resistance of the titanium silicide. First, a silicon substrate with an exposed crystalline silicon layer on the surface is provided. Then a titanium layer and a titanium nitride layer are sequentially formed. Finally, using a rapid thermal processing, an epitaxial titanium silicide layer is formed.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: March 24, 1998
    Assignee: United Microelectronics Corporation
    Inventors: Jiunn Hsien Lin, Shuh-Ren Chen