Patents by Inventor Jiunn-Jyi Lin
Jiunn-Jyi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7015129Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.Type: GrantFiled: November 29, 2004Date of Patent: March 21, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
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Publication number: 20050095836Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.Type: ApplicationFiled: November 29, 2004Publication date: May 5, 2005Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
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Patent number: 6844626Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.Type: GrantFiled: May 23, 2003Date of Patent: January 18, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
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Publication number: 20040235223Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.Type: ApplicationFiled: May 23, 2003Publication date: November 25, 2004Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
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Patent number: 5629237Abstract: A method is described for forming tapered contact via holes in large scale integrated circuit structures which avoids the formation of a re-entrance profile. The re-entrance profile can form at the entrance to the contact via hole when a dry etch is used as a first etching step by redepositing material removed during the dry etch at the entrance of the contact via hole. This re-entrance profile makes the angle of entrance into the contact via hole greater than 90.degree. and the step coverage of metal filling the hole poor. This invention uses wet etching with a greater lateral etch rate than vertical etch rate as a first etching step in the formation of the contact via hole and avoids the formation of the re-entrance profile. The edges of the resulting contact via hole are smooth and the entrance angle into the contact via hole is substantially less than 90.degree.. The step coverage of metal later filling the contact via hole is substantially improved.Type: GrantFiled: October 19, 1995Date of Patent: May 13, 1997Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Pei-Jan Wang, Kuei-Lung Chou, Jiunn-Jyi Lin, Hsien-Wen Chang
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Patent number: 5461254Abstract: There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer.Type: GrantFiled: December 6, 1994Date of Patent: October 24, 1995Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Lih-Shyng Tsai, Jiunn-Jyi Lin, Kwang-Ming Lin, Shu-Lan Ying
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Patent number: 5334554Abstract: A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within semiconductor substrate electrically separating certain of these source/drain regions from one another are provided. A passivation layer is formed over the surfaces of said patterns.Type: GrantFiled: January 24, 1992Date of Patent: August 2, 1994Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kwang-Ming Lin, Lih-Shyig Tsai, Jiunn-Jyi Lin, Yung-Haw Liaw
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Patent number: 5286667Abstract: The method is described for fabricating an integrated circuit having a combination of a capacitor and metal oxide semiconductor field effect transistor with gate electrodes and source/drain regions. The method features the use of silicon nitride or silicon oxynitride barrier layers. The barrier layer is a key to the successful lightly doped drain spacer etch process. The barrier layer aids in endpoint detection for the plasma etch. This allows for less loss of the field oxide and greater thickness control of the field oxide regions. Further, the silicon nitride endpoint detection allows for the removal of undesirable residual silicon oxide from the surface of the capacitor plate without loss of the polysilicon capacitor plate itself.Type: GrantFiled: August 11, 1992Date of Patent: February 15, 1994Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jiunn-Jyi Lin, Lih-Shyng Tsai, Hsien-Wen Chang, Chang-Tai Chiao
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Patent number: 5252515Abstract: A multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer.Type: GrantFiled: August 12, 1991Date of Patent: October 12, 1993Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Lih-Shyng Tsai, Jiunn-Jyi Lin, Kwang-Ming Lin, Shu-Lan Ying
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Patent number: 5248384Abstract: The method of forming a void-free surface on aluminum-copper metallurgy after stripping of resist is described. There is provided an aluminum-copper metallurgy on a suitable substrate, such as a semiconductor integrated circuit wafer during manufacture. A resist layer is formed over surface. The resist layer is exposing, developing and the developed resist is used as an etch mask to etch a layer, such as an insulating layer on the metallurgy which results in exposing the aluminum-copper metallurgy surface. The resist etch mask is removed by plasma oxygen ashing in presence of the exposed aluminum-copper surface. Rapid thermal annealing of the aluminum-copper metallurgy at a temperature of between about 400.degree. to 550.degree. C. is performed. The resulting surfaces are rinsed to remove any residual resist material. The result is a void-free aluminum-copper metallurgy surface.Type: GrantFiled: December 9, 1991Date of Patent: September 28, 1993Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kwang-Ming Lin, Lih-Shyng Tsai, Jiunn-Jyi Lin, Chin-Twan Wei