Patents by Inventor Jiunn-Yau Liou

Jiunn-Yau Liou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5701071
    Abstract: Systems for controlling the current consumption of an integrated circuit chip and the like so as to reduce the inductive voltage drops occurring over the power supply lines within the chip and power supply lines to the chip are disclosed. The systems according to the present invention are applicable to circuits having two or more sub-circuits formed on a semiconductor substrate, each sub-circuit having two or more power supply inputs. An exemplary system comprises two or more current shunting elements formed on the substrate, with each current shunting element coupled in parallel with the power supply inputs of a selected sub-circuit. The system has at least two main power supply lines formed on the semiconductor substrate, with each selected sub-circuit having each of its power supply inputs coupled to a main power supply line. A current shunting element may comprise a Zener diode, an active shunt circuit, or equivalents thereof.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: December 23, 1997
    Assignee: Fujitsu Limited
    Inventors: Jiunn-Yau Liou, Richard L. Wheeler, Bidyut Sen, James C. Parker, Jr.
  • Patent number: 4917451
    Abstract: An electro-optic waveguide structure having a single mode channeled waveguide pattern of the Mach-Zehnder configuration is formed in a substrate of potassium titanyl phosphate.
    Type: Grant
    Filed: January 19, 1988
    Date of Patent: April 17, 1990
    Assignee: E. I. DuPont de Nemours and Company
    Inventors: Michael P. Chouinard, Edward P. Gargiulo, James L. Hohman, Jr., Daniel B. Laubacher, Jiunn-Yau Liou, Moshe Oren
  • Patent number: 4789967
    Abstract: An apparatus for storing data for read and write access receiving reset control signals, comprising a plurality of storage blocks, each block including an array of memory units for storing a unit of data is provided that is reset along storage block boundaries. A reset control means, coupled to receive the reset control signals which identify at least one of the storage blocks, is included for generating block reset signals. A means, coupled to the memory units in each storage block and to receive the block reset signals, for resetting the identified block of memory to 0. .
    Type: Grant
    Filed: September 16, 1986
    Date of Patent: December 6, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jiunn-Yau Liou, May-Lin Lee, Moon S. Kok, James Yu, Aloysius T. Tam
  • Patent number: 4769791
    Abstract: The circuit provides one or several banks of capacitors, the capacitors in each bank being identical in size. A single fuse for each bank of capacitors controls the connection of the capacitors to a pulse-width-determining node on each of the ATD (address-transition-detect) pulse generators of the SRAM device. Depending on the position of the fuse in the circuit, the blowing of a single fuse can either add to the capacitance at the ATD nodes or substract from it. Thus the pulse-width of all ATD pulse generators can be adjusted shorter or longer simultaneously by blowing a single fuse only.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: September 6, 1988
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jiunn-Yau Liou, May-Lin Lee, Moon S. Kok, Gary Chang