Patents by Inventor Jiuun-Jer Yang
Jiuun-Jer Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9299622Abstract: A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage.Type: GrantFiled: July 3, 2014Date of Patent: March 29, 2016Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Jiuun-Jer Yang
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Publication number: 20150079706Abstract: A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage.Type: ApplicationFiled: July 3, 2014Publication date: March 19, 2015Inventor: Jiuun-Jer Yang
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Patent number: 8796685Abstract: A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage.Type: GrantFiled: February 25, 2011Date of Patent: August 5, 2014Assignee: Semiconductor Manufacturing (Shanghai) CorporationInventor: Jiuun-Jer Yang
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Publication number: 20110215393Abstract: A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage.Type: ApplicationFiled: February 25, 2011Publication date: September 8, 2011Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: JIUUN-JER YANG
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Patent number: 6215156Abstract: A transistor formed in a semiconductor substrate having improved ESD protection. The transistor includes a gate structure formed atop of a semiconductor substrate. First and second sidewall spacers are formed on the sidewalls of the gate structure. A lightly doped source region is formed in said semiconductor substrate and substantially underneath only the first sidewall spacer. A source region is formed in said semiconductor substrate and adjacent to the first sidewall spacer and a drain region is formed in said semiconductor substrate and adjacent to the second sidewall spacer. A first ESD implant is provided that overlaps the source region and extending underneath the first sidewall spacer. A second ESD implant is formed to overlap the drain region and extending underneath the second sidewall spacer. Preferably, the ESD implants are formed using an angled ion implantation technique.Type: GrantFiled: August 2, 1999Date of Patent: April 10, 2001Assignee: Taiwan Semiconductor Manufacturing CorporationInventor: Jiuun-Jer Yang
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Patent number: 6051984Abstract: A wafer-level method is provided for hot-carrier reliability testing a plurality of MOS transistors formed in a semiconductor wafer. The MOS transistors in the semiconductor wafer are divided into at least three groups, including a first group, a second group, and a third group. A built-in multi-voltage supplier is integrally formed along with the MOS transistors undergoing testing in the same semiconductor wafer. This built-in multi-voltage supplier is devised in such a manner as to divide an input voltage into at least four testing voltages, including a first drain voltage, a second drain voltage, a third drain voltage, and a gate voltage.Type: GrantFiled: November 6, 1997Date of Patent: April 18, 2000Assignee: Winbond Electronics Corp.Inventors: Honda Huang, Jiuun-Jer Yang
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Patent number: 6051482Abstract: A method for manufacturing a buried-channel pMOSFET device that utilizes a plasma doping technique to form a very shallow P-type channel layer on the top surface of a sub-micron buried-channel pMOSFET. The buried-channel pMOSFET device formed by the method has a higher current drivability and a higher anti-punchthrough resistance.Type: GrantFiled: February 17, 1998Date of Patent: April 18, 2000Assignee: Winbond Electronics Corp.Inventor: Jiuun-Jer Yang
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Patent number: 6040603Abstract: A transistor formed in a semiconductor substrate having improved ESD protection is disclosed. The transistor includes a first ESD implant formed underneath the source region and the drain region of the transistor. The first ESD implant has the same impurity type as the source region and the drain region. Further, a second ESD implant is formed underneath the first ESD implant, the second ESD implant having an impurity type opposite to that of said first ESD implant. The second ESD implant also is spaced apart vertically from the first ESD implant.Type: GrantFiled: April 30, 1999Date of Patent: March 21, 2000Assignee: Worldwide Semiconductor Manufacturing CorporationInventor: Jiuun-Jer Yang
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Patent number: 5763285Abstract: A process for forming a lightly-doped drain (LDD) structure in a MOSFET or other semiconductor device. A first polysilicon layer is deposited over a thin gate oxide layer formed on a substrate. The first polysilicon layer is etched to form a first gate region. The substrate is then doped adjacent the gate region to form a drain region having a relatively low impurity concentration. The first polysilicon gate region is removed and a second polysilicon layer is applied to the substrate. The second layer is etched to form a second gate region which will serve as the actual gate region for the MOSFET device. The drain region is then doped a second time to form an LDD structure in which a portion of the drain region underlying the second gate region remains lightly doped while another portion of the drain region exposed to the second doping becomes more heavily doped. The difference in length between the first and second gate regions is used to set the gate/drain overlapped length.Type: GrantFiled: June 10, 1996Date of Patent: June 9, 1998Assignee: Winbond Electronics CorporationInventor: Jiuun-Jer Yang