Patents by Inventor JIUXUAN LIU

JIUXUAN LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220147684
    Abstract: A stencil step design method and system, a computer readable storage medium and a device. The method comprises: acquiring data of stencil apertures for electronic components in a circuit board, and identifying the stencil apertures for electronic components one by one to determine whether the stencil apertures need to be stepped; and if yes, performing step design for the stencil apertures that need to be stepped according to preset step rules corresponding to the stencil apertures for electronic components one by one so as to generate a stencil step design file with the step design, and outputting the stencil step design file. According to the present disclosure, 90% or more steps can be automatically designed and the stencil step design is in conformity with processing requirements. A manual intervention process is omitted, and the design can be accomplished by several simple steps.
    Type: Application
    Filed: December 18, 2019
    Publication date: May 12, 2022
    Applicant: VAYO (SHANGHAI) TECHNOLOGY CO., LTD.
    Inventors: JISHUO LIU, JIUXUAN LIU, YONGQIANG SONG, YONGJIAN QU, SHENGJIE QIAN
  • Patent number: 10824785
    Abstract: A PCB stencil manufacturing method and system. The method comprises: inputting PCB stencil design information in a preset input format, the PCB stencil design information comprises solder pad element information; and converting the PCB stencil design information into corresponding system core data information, the system core data information comprises solder pad element packaging information, and the solder pad element packaging information comprises a solder pad element packaging pattern and solder pad element coordinates; and querying a stencil opening database according to the solder pad element packaging pattern, records in the stencil opening database comprise the following attributes: a solder pad element packaging pattern and a stencil opening pattern; and placing a stencil opening pattern corresponding to a matching solder pad element packaging pattern to an opening layer according to the solder pad element coordinates.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: November 3, 2020
    Assignee: VAYO (SHANGHAI) TECHNOLOGY CO., LTD.
    Inventors: Shengjie Qian, Fengshou Liu, Jiuxuan Liu, Jishuo Liu
  • Publication number: 20190012421
    Abstract: A PCB stencil manufacturing method and system. The method comprises: inputting PCB stencil design information in a preset input format, the PCB stencil design information comprises solder pad element information; and converting the PCB stencil design information into corresponding system core data information, the system core data information comprises solder pad element packaging information, and the solder pad element packaging information comprises a solder pad element packaging pattern and solder pad element coordinates; and querying a stencil opening database according to the solder pad element packaging pattern, records in the stencil opening database comprise the following attributes: a solder pad element packaging pattern and a stencil opening pattern; and placing a stencil opening pattern corresponding to a matching solder pad element packaging pattern to an opening layer according to the solder pad element coordinates.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 10, 2019
    Applicant: VAYO (SHANGHAI) TECHNOLOGY CO., LTD.
    Inventors: SHENGJIE QIAN, FENGSHOU LIU, JIUXUAN LIU, JISHUO LIU