Patents by Inventor Jiuzhou Tang

Jiuzhou Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Predicting defect rate based on lithographic model parameters
    Patent number: 11914306
    Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: February 27, 2024
    Assignee: Synopsys, Inc.
    Inventors: Erik A. Verduijn, Ulrich Karl Klostermann, Ulrich Welling, Jiuzhou Tang, Hans-Jürgen Stock
  • LARGE SCALE COMPUTATIONAL LITHOGRAPHY USING MACHINE LEARNING MODELS
    Publication number: 20220392191
    Abstract: A computational lithography process uses machine learning models. An aerial image produced by a lithographic mask is first calculated using a two-dimensional model of the lithographic mask. This first aerial image is applied to a first machine learning model, which infers a second aerial image. The first machine learning model was trained using a training set that includes aerial images calculated using a more accurate three-dimensional model of lithographic masks. The two-dimensional model is faster to compute than the three-dimensional model but it is less accurate. The first machine learning model mitigates this inaccuracy.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 8, 2022
    Inventors: Dereje Shewaseged Woldeamanual, Thomas Heribert Mülders, Jiuzhou Tang, Rainer Zimmermann, Robert Marshall Lugg, Hans-Jürgen Stock, Georg Albert Viehöver
  • PREDICTING DEFECT RATE BASED ON LITHOGRAPHIC MODEL PARAMETERS
    Publication number: 20210116817
    Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.
    Type: Application
    Filed: October 16, 2020
    Publication date: April 22, 2021
    Applicant: Synopsys, Inc.
    Inventors: Erik A. Verduijn, Ulrich Karl Klostermann, Ulrich Welling, Jiuzhou Tang, Hans-Jürgen Stock