Abstract: A microelectronic device having a stack structure with an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks has a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure has staircase structures each having steps with edges of the tiers of the stack structure. The filled trench has a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures have first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions that the first protrusions.

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. The first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. An insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. Individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. The insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. Insulative material is formed in the cavity directly above the insulating lining. Conductive vias are formed through the insulative material and the insulating lining.

Abstract: A variety of applications can include apparatus having a memory device structured with a three-dimensional array of memory cells and one or more vertical metal contacts extending through levels of the memory device, where the one or more vertical metal contacts are formed with reduced stress. Each of the one or more vertical metal contacts can be constructed by forming a liner on walls of an opening in a dielectric, where the opening extends through the levels for the memory device, and forming a metal composition adjacent the liner and filling the opening with the metal composition. The liner can be removed from at least a portion of the walls of the dielectric, where the liner has a composition correlated to the metal composition such that removal of the liner reduces stress on the metal composition.

Abstract: A microelectronic device includes a stack structure comprising blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks comprising a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers; and a filled trench vertically overlying and within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench includes a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions and at least one dielectric structure doped with one or more of carbon and boron on the dielectric liner material, the at least one dielectric structure horizontally overlapping the steps of the stadium structure.

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs in a first vertical cross-section along a first direction. Insulating material is in the cavity above the flight of stairs. The insulating material comprises first material atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. Insulative second material of different composition from that of the first material is directly above the first material. The first material has an uppermost surface in the cavity that is below an uppermost surface of the insulative second material in the cavity.

Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

Abstract: An electronic device comprises a stack structure comprising tiers of alternating conductive structures and insulative structures, staircase structures within the stack structure and including steps defined by edges of the tiers, contacts on the steps of the staircase structures, support pillars extending vertically through the stack structure, and support structures laterally adjacent to the contacts in a first horizontal direction and extending vertically through the stack structure. The support pillars exhibit a lateral dimension relatively larger than a lateral dimension of the contacts and the support structures. Related methods, memory devices, and systems are also described.

Abstract: A microelectronic device comprises stack structure comprising an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks comprises a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure comprises staircase structures each having steps comprising edges of the tiers of the stack structure. The filled trench comprises a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures comprise first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions than the first protrusions.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.

Abstract: An electronic device comprises a stack structure comprising tiers of alternating conductive structures and insulative structures, staircase structures within the stack structure and including steps defined by edges of the tiers, contacts on the steps of the staircase structures, support pillars extending vertically through the stack structure, and support structures laterally adjacent to the contacts in a first horizontal direction and extending vertically through the stack structure. The support pillars exhibit a lateral dimension relatively larger than a lateral dimension of the contacts and the support structures. Related methods, memory devices, and systems are also described.

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. At least a portion of sidewalls of the cavity is lined with sacrificial material. Insulative material is formed in the cavity radially inward of the sacrificial material. At least some of the sacrificial material is removed from being between the cavity sidewalls and the insulative material to form a void space there-between. Insulator material is formed in at least some of the void space. Other embodiments, including structure independent of method, are disclosed.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.