Patents by Inventor Jiwan Koo

Jiwan Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006190
    Abstract: A method of manufacturing a semiconductor device includes forming a channel layer on a substrate, forming a mask on the channel layer, surface-treating an exposed surface of the channel layer exposed from the mask, forming an electrode on the exposed surface of the channel layer, and removing the mask. The channel layer includes a two-dimensional material, and the surface-treating of the exposed surface of the channel layer includes surface-treating the exposed surface of the channel layer with HCl.
    Type: Application
    Filed: March 6, 2023
    Publication date: January 4, 2024
    Applicants: SAMSUNG ELECTRONICS CO., LTD, RESEARCH & BUSINESS FOUNDATION OF SUNGKYEUNGAM UNIVERSITY
    Inventors: Jin-Hong PARK, Hogeun AHN, BoReum LEE, Sunguk JANG, Jiwan KOO, Seunghwan SEO
  • Publication number: 20230317811
    Abstract: A semiconductor device includes a channel on a substrate, the channel including a two-dimensional (2D) material, a gate insulating layer on a portion of the channel, a gate electrode on the gate insulating layer, first and second contact patterns on respective portions of the channel, the first and second contact patterns including a carbide of a transition metal, and first and second source/drain electrodes on the first and second contact patterns, respectively, and the first and second source/drain electrodes including a metal.
    Type: Application
    Filed: November 17, 2022
    Publication date: October 5, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinhong PARK, Jiwan KOO, Sahwan HONG, Juncheol KANG, Seunghwan SEO, Hogeun AHN, Jaewoong CHOI, Bongjin KUH
  • Publication number: 20230290870
    Abstract: A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.
    Type: Application
    Filed: August 16, 2022
    Publication date: September 14, 2023
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Jinhong PARK, Jiwan Koo, Maksim ANDREEV, Sahwan HONG, Seunghwan SEO, Juhee LEE, Bongjin KUH