Patents by Inventor JIWEI WEN

JIWEI WEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10977521
    Abstract: The present invention relates to the field of pedestrian detection, and particularly relates to a multi-scale aware pedestrian detection method based on an improved full convolutional network. Firstly, a deformable convolution layer is introduced in a full convolutional network structure to expand a receptive field of a feature map. Secondly, a cascade-region proposal network is used to extract multi-scale pedestrian proposals, discriminant strategy is introduced, and a multi-scale discriminant layer is defined to distinguish pedestrian proposals category. Finally, a multi-scale aware network is constructed, a soft non-maximum suppression algorithm is used to fuse the output of classification score and regression offsets by each sensing network to generate final pedestrian detection regions.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 13, 2021
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Li Peng, Hui Liu, Jiwei Wen, Linbai Xie
  • Publication number: 20210056351
    Abstract: The present invention relates to the field of pedestrian detection, and particularly relates to a multi-scale aware pedestrian detection method based on an improved full convolutional network. Firstly, a deformable convolution layer is introduced in a full convolutional network structure to expand a receptive field of a feature map. Secondly, a cascade-region proposal network is used to extract multi-scale pedestrian proposals, discriminant strategy is introduced, and a multi-scale discriminant layer is defined to distinguish pedestrian proposals category. Finally, a multi-scale aware network is constructed, a soft non-maximum suppression algorithm is used to fuse the output of classification score and regression offsets by each sensing network to generate final pedestrian detection regions.
    Type: Application
    Filed: June 27, 2018
    Publication date: February 25, 2021
    Inventors: Li PENG, Hui LIU, Jiwei WEN, Linbai XIE
  • Patent number: 10897810
    Abstract: The present invention provides a high speed signal fan-out method for BGA and a PCB using the same. The method comprises: providing a printed circuit board (PCB), providing a plurality of vias and signal traces of the vias on the PCB; and providing back-drilled holes for routing of other signal traces at positions corresponding to the vias. The vias are arranged into a plurality of straight lines from an edge to the center of the PCB. The plurality of straight lines each is horizontal or vertical. The signal traces of the vias in a straight line are arranged from high to low or from low to high with respect to routing positions of the vias, and the back-drilled holes of the plurality of vias are arranged in descending or ascending order corresponding to the depths of the back-drilled holes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 19, 2021
    Assignee: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO. LTD
    Inventors: Jiwei Wen, Chenxia Feng, Liang Chen, Lijuan Qu
  • Publication number: 20190208618
    Abstract: The present invention provides a high speed signal fan-out method for BGA and a PCB using the same. The method comprises: providing a printed circuit board (PCB), providing a plurality of vias and signal traces of the vias on the PCB; and providing back-drilled holes for routing of other signal traces at positions corresponding to the vias. The vias are arranged into a plurality of straight lines from an edge to the center of the PCB. The plurality of straight lines each is horizontal or vertical. The signal traces of the vias in a straight line are arranged from high to low or from low to high with respect to routing positions of the vias, and the back-drilled holes of the plurality of vias are arranged in descending or ascending order corresponding to the depths of the back-drilled holes.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 4, 2019
    Applicant: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO. LT D
    Inventors: JIWEI WEN, CHENXIA FENG, LIANG CHEN, LIJUAN QU
  • Publication number: 20190208633
    Abstract: The present invention provides a signal trace fan-out method for double-sided mounting on a PCB, including: respectively providing one or more blind vias on the top-layer surface and the bottom-layer surface of a PCB; and fanning out, through each of the blind vias, one or more signal traces of to-be-mounted components on the top-layer surface and the bottom-layer surface of the PCB. The number and positions of the blind vias are set based on the size of routing space when the to-be-mounted component is mounted on the top-layer surface or the bottom-layer surface of the PCB. In a manner of combining the blind vias with through holes, the present invention achieves successful fan-out of the signal traces when QSFP-DD connectors are mounted at same positions on both the top layer and the bottom layer of the PCB, and ensures relatively good signal integrality.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 4, 2019
    Applicant: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO. LTD
    Inventors: JIWEI WEN, CHENXIA FENG, LIANG CHEN, LIJUAN QU