Abstract: An air conditioner may include: a compressor configured to compress a refrigerant; an expansion valve configured to expand the compressed refrigerant; and a controller, comprising circuitry, configured to: based on receiving a command to execute a low-power mode, change an operating frequency of the compressor to an operating frequency corresponding to the low-power mode, and change an opening degree of the expansion valve to a temporary stabilization opening degree, and change from the temporary stabilization opening degree to a final stabilization opening degree.

Abstract: An air conditioner includes: a housing, a compressor disposed inside the housing and configured to compress a refrigerant, a first heat exchanger disposed inside the housing and configured to exchange heat with outdoor air, a second heat exchanger disposed inside the housing and configured to exchange heat with indoor air, a refrigerant pipe connecting the compressor and the second heat exchanger and configured to allow the refrigerant to flow therein, and a charging pipe configured to charge the refrigerant pipe with the refrigerant. The refrigerant pipe includes a first sub-pipe and a second sub-pipe connected to the second heat exchanger to receive the refrigerant passed through the second heat exchanger. The refrigerant pipe includes a main pipe connected to the compressor to allow the refrigerant passed through the first sub-pipe and the second sub-pipe to be combined. The charging pipe may be configured to be connected to the first sub-pipe.

Abstract: An air conditioner may include: an evaporator; a base disposed below the evaporator; a scattering wheel configured to scatter water stored in the base; a wheel drive motor configured to rotate the scattering wheel; a first water level sensor and a second water level sensor configured to detect a water level of the water stored in the base; and a controller configured to control a rotational speed of the wheel drive motor based on detection results of the first water level sensor and the second water level sensor.

Abstract: A semiconductor package includes a substrate including bonding pads, semiconductor chips stacked on the substrate and each including a lower surface and an upper surface, and connection pads on the upper surface, connection films spaced apart from each other in a first direction, the connection films electrically connecting the connection pads and corresponding ones of the bonding pads to each other in a second direction intersecting the first direction, a mold covering the semiconductor chips and the connection films, and connection bumps being under the substrate, the connection bumps electrically connected to the bonding pads. Each of the connection films includes a flexible film covering at least two connection pads adjacent to each other in the first direction, among the connection pads, and conductive lines extending in the second direction on the flexible film, the conductive lines respectively connected to the at least two connection pads.

Abstract: Provided is a mounting substrate for a semiconductor package, including a substrate having an upper surface and a lower surface opposite to each other, the substrate including a plurality of insulation layers and wirings in the plurality of insulation layers, first substrate pads and second substrate pads on the upper surface in a chip mounting region of the mounting surface, heat absorbing pads on the upper surface in a peripheral region of the mounting surface adjacent to the chip mounting region, and connection lines in the substrate, the connection lines being configured to thermally couple the heat absorbing pads and the second substrate pads to each other.

Abstract: An injection-locked clock multiplier includes an oscillator control unit configured to output an injection clock signal with a frequency of N times a reference clock signal, an error detector configured to detect a frequency error indicating whether a frequency of the injection clock signal corresponds to the N times the frequency of the reference clock signal in a first operation mode and configured to detect an error due to injection path non-ideality from the injection clock signal in a second operation mode, and an error adjuster configured to receive one of information on the frequency error and information on the error due to the injection path non-ideality from the error detection unit and configured to adjust an operation frequency of the oscillator based on the frequency error or configured to adjust an operation cycle of the oscillator based on the error due to the injection path non-ideality.

Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, the semiconductor chip including a first surface facing the lower substrate and a second surface opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip, the upper substrate including a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of the semiconductor chip and the connection structure; and adhesive members disposed on the second surface of the semiconductor chip such as to correspond to the support members, respectively, the adhesive members disposed in contact with the second surface and the support members.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a package substrate, a plurality of semiconductor dies stacked on the package substrate wherein end portions of the semiconductor dies form a stepwise shape, a plurality of wires that connect the semiconductor dies to the package substrate, and a mold layer that covers the package substrate, the semiconductor dies, and the wires. Each of the semiconductor dies includes a die substrate, a die dielectric layer on the die substrate, a bonding pad on the die dielectric layer, and a first polymer layer that covers the die dielectric layer and exposes the bonding pad. A plurality of oxygen atoms are between the semiconductor dies.

Abstract: A semiconductor package includes a package substrate including an insulating layer, an interconnection circuit, and upper pads and lower pads electrically connected through the interconnection circuit, a plurality of semiconductor chips stacked including connection pads, a support structure contacting a side surface of a first semiconductor chip, which is an uppermost one among the plurality of semiconductor chips and at least a portion of an upper surface of a second semiconductor chip, which is one among the plurality of semiconductor chips below the first semiconductor chip, a first connection structure connecting the upper pads of the package substrate to the connection pads of the second semiconductor chip, a second connection structure connecting the connection pads of the first semiconductor chip to the connection pads of the second semiconductor chip, and an encapsulant covering the plurality of semiconductor chips, the first connection structure, and the second connection structure.

Abstract: Provided is a mounting substrate for a semiconductor package, including a substrate having an upper surface and a lower surface opposite to each other, the substrate including a plurality of insulation layers and wirings in the plurality of insulation layers, first substrate pads and second substrate pads on the upper surface in a chip mounting region of the mounting surface, heat absorbing pads on the upper surface in a peripheral region of the mounting surface adjacent to the chip mounting region, and connection lines in the substrate, the connection lines being configured to thermally couple the heat absorbing pads and the second substrate pads to each other.

Abstract: A semiconductor package includes a package substrate including substrate pads on an upper portion of the package substrate, a first semiconductor chip on the package substrate, a first chip pad on the first semiconductor chip, a first conductive connection pattern on an upper surface of the first chip pad, an upper surface of the first semiconductor chip, and an upper surface of a first substrate pad among the substrate pads, and a first insulation layer on the package substrate and covering the first semiconductor chip, the first chip pad and the first conductive connection pattern.

Abstract: A semiconductor package includes a package substrate including upper pads, semiconductor chips stacked in a first direction and each semiconductor chip including bonding pad structures respectively disposed at one side of an upper surface thereof and spaced apart from each other in a second direction, first connection bumps on the bonding pad structures, each first connection bump electrically connected to a respective bonding pad structure, second connection bumps on the upper pads, each second connection bump electrically connected to a corresponding bonding pad structure and a corresponding upper pad, an interconnection pattern extending in a third direction on the package substrate and the semiconductor chips and electrically connecting each of the first connection bumps at each level to a corresponding first connection bump located at a different level.

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

Abstract: A semiconductor package includes a package substrate, an encapsulation structure stacked on the package substrate, a plurality of conductive bumps disposed between the package substrate and the encapsulation structure, and an adhesive layer attaching the package substrate and the encapsulation structure to each other. The encapsulation structure includes a sealing member having an upper surface and a lower surface opposite to each other, a plurality of semiconductor chips sequentially arranged in the sealing member such that a front surface on which chip pads are formed faces the package substrate, and conductive wires extending from a lower surface of the sealing member to the chip pads of the plurality of semiconductor chips. The plurality of conductive bumps are disposed between the conductive wires and substrate pads of the package substrate.

Abstract: A semiconductor package and a method of manufacturing the same are provided, in which a height and a one-dimensional area of the semiconductor package may be reduced. The semiconductor package includes a package substrate, a chip stack structure including at least two semiconductor chips aligned with one another and stacked on the package substrate in a vertical direction, each of the at least two semiconductor chips including chip pads exposed at a side surface thereof, an anisotropic conductive film (ACF) covering a side surface of the chip stack structure, and a conductive pattern film covering the ACF and including a conductive pattern connecting the chip pads to a substrate pad of the package substrate.

Abstract: A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

Abstract: A method of manufacturing a semiconductor chip includes grinding a substrate that includes a device region and a scribe lane region, forming a protective coating layer on the substrate, plasma-thinning the substrate, and plasma-sawing the scribe lane region of the substrate. The plasma-thinning of the substrate and the plasma-sawing of the scribe lane region of the substrate are performed in-situ in a same chamber.

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

Abstract: An injection-locked clock multiplier includes an oscillator control unit configured to output an injection clock signal with a frequency of N times a reference clock signal, an error detector configured to detect a frequency error indicating whether a frequency of the injection clock signal corresponds to the N times the frequency of the reference clock signal in a first operation mode and configured to detect an error due to injection path non-ideality from the injection clock signal in a second operation mode, and an error adjuster configured to receive one of information on the frequency error and information on the error due to the injection path non-ideality from the error detection unit and configured to adjust an operation frequency of the oscillator based on the frequency error or configured to adjust an operation cycle of the oscillator based on the error due to the injection path non-ideality.

Abstract: Disclosed are a method of determining properties of a service executed in a user terminal based on packet analysis, and a user terminal and a computer program that perform the same. The method of determining properties of a service executed in a user terminal based on packet analysis according to various embodiments of the present invention is performed by the user terminal, which includes identifying an analysis target packet among packets generated as a service is executed through the user terminal, and determining the properties of the service by analyzing the identified analysis target packet.