Patents by Inventor Jixiang Chen

Jixiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12670879
    Abstract: A display panel includes a display area and a peripheral area. The peripheral area includes a first signal line arrangement region including first signal lines and a second signal line arrangement region including second signal lines. First lead-out lines are led out from the first lead-out positions included in a border of the first signal line arrangement region and are connected to the first signal lines. A first lead-out line is connected to a data line. A first reference signal line is led out from a first reference lead-out position and connected to a first reference data line. Second lead-out lines are led out from second lead-out positions included in a border of the second signal line arrangement region, and are electrically connected to the second signal lines; and second lead-out line is electrically connected to a gate line.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: June 30, 2026
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xin Fang, Wenchao Wang, Xu Xu, Jinliang Wang, Zecun Zeng, Tianyang Han, Xiaolong Chen, Jixiang Chen, Longgan Hu
  • Publication number: 20260112327
    Abstract: A display panel includes a display area and a peripheral area. The peripheral area includes a first signal line arrangement region including first signal lines and a second signal line arrangement region including second signal lines. First lead-out lines are led out from the first lead-out positions included in a border of the first signal line arrangement region and a are connected to the first signal lines. A first lead-out line is connected to a data line. A first reference signal line is led out from a first reference lead-out position and connected to a first reference data line. Second lead-out lines are led out from second lead-out positions included in a border of the second signal line arrangement region, and are electrically connected to the second signal lines; a second lead-out line is electrically connected to a gate line.
    Type: Application
    Filed: September 23, 2022
    Publication date: April 23, 2026
    Inventors: Xin Fang, Wenchao Wang, Xu Xu, Jinliang Wang, Zecun Zeng, Tianyang Han, Xiaolong Chen, Jixiang Chen, Longgan Hu
  • Patent number: 12601943
    Abstract: Provided are a display panel and a preparation method thereof and a display device. The display panel includes an array substrate, where the array substrate includes a first base, a first signal wire layer located on a side of the first base and an anti-reflection layer located between the first signal wire layer and the first base. The display panel further includes a display region and a non-display region; the first signal wire layer includes a first signal wire located in the display region, and the anti-reflection layer includes a first anti-reflection structure located in the display region and a second anti-reflection structure located in the non-display region. An orthographic projection of the first anti-reflection structure on a plane where the first base is located covers at least part of an orthographic projection of the first signal wire on the plane where the first base is located.
    Type: Grant
    Filed: April 26, 2024
    Date of Patent: April 14, 2026
    Assignee: Xiamen Tianma Optoelectronics Co., Ltd.
    Inventors: Wenxing Xi, Jixiang Chen, Xuhui Peng, Qiaoning Zheng, Hongyuan Huang, Xiaolin Wang, Wei Huang
  • Publication number: 20260018105
    Abstract: A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.
    Type: Application
    Filed: September 24, 2025
    Publication date: January 15, 2026
    Inventors: Xin FANG, Wenchao WANG, Sangjin PARK, Jixiang CHEN, Xiaolong CHEN, Lixia ZHANG
  • Patent number: 12517404
    Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel comprises: a base substrate having multiple rows and multiple columns of sub-pixels; and a pixel electrode layer located on the base substrate, the pixel electrode layer comprising a plurality of pixel electrodes arranged apart from each other, and one sub-pixel comprising one pixel electrode, wherein the pixel electrode comprises: a first electrode strip and comb structures respectively connected to both sides of the first electrode strip, each comb structure consisting of a plurality of second electrode strips and a plurality of slits arranged alternately.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: January 6, 2026
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Baoqiang Wang, Xu Xu, Wenchao Wang, Shanshan Xu, Jinliang Wang, Xin Fang, Jixiang Chen
  • Patent number: 12494181
    Abstract: A display substrate includes a base substrate, a first drive module, a second drive module, an array of sub-pixel circuits, rows of gate lines, and columns of data lines. A portion of sub-pixel circuits having a first color in the same row are electrically connected to one row of the gate line, another portion of sub-pixel circuits having the first color in the same row are electrically connected to another row of the gate line. The first drive module is electrically connected to a first end of the row of gate line and the second drive module is electrically connected to a second end of the another row of gate line. The first end and the second end are opposite ends. In the sub-pixel circuits located in the same row, at least two sub-pixel circuits at the same side of the data line are electrically connected to the data line.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: December 9, 2025
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Sangjin Park, Jixiang Chen, Wenchao Wang, Jinliang Wang, Xin Fang, Xu Xu, Shanshan Xu
  • Patent number: 12451046
    Abstract: A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: October 21, 2025
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Xin Fang, Wenchao Wang, Sangjin Park, Jixiang Chen, Xiaolong Chen, Lixia Zhang
  • Publication number: 20250248125
    Abstract: An array substrate of this disclosure includes: a substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate; orthographic projections of the first and second conductive layers on the substrate have an overlapping region; portions of the first and second conductive layers in the overlapping region constitute a first conductive pattern; a portion of the first conductive layer outside the overlapping region includes a second conductive pattern and a third conductive pattern; the second and third conductive patterns have an interval therebetween. A first distance between first regions of the second and third conductive patterns proximal to the first conductive pattern is larger than a second distance between second regions of the second and third conductive patterns distal to the first conductive pattern.
    Type: Application
    Filed: April 21, 2025
    Publication date: July 31, 2025
    Inventors: Jinliang WANG, Chen LIN, Jixiang CHEN, Wenchao WANG
  • Patent number: 12317593
    Abstract: An array substrate of this disclosure includes: a substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate; orthographic projections of the first and second conductive layers on the substrate have an overlapping region; portions of the first and second conductive layers in the overlapping region constitute a first conductive pattern; a portion of the first conductive layer outside the overlapping region includes a second conductive pattern and a third conductive pattern; the second and third conductive patterns have an interval therebetween. A first distance between first regions of the second and third conductive patterns proximal to the first conductive pattern is larger than a second distance between second regions of the second and third conductive patterns distal to the first conductive pattern.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 27, 2025
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinliang Wang, Chen Lin, Jixiang Chen, Wenchao Wang
  • Patent number: 12290950
    Abstract: A cutting method of a display panel comprises: along a first cutting line (A), cutting a color-film substrate of a to-be-cut display panel (501); and along a second cutting line (B), cutting an array substrate of the to-be-cut display panel to obtain a display panel; wherein, in a target direction parallel to the to-be-cut display panel, the second cutting line (B) is located between the first cutting line (A) and a display region of the to-be-cut display panel, and in the target direction, a distance between the first cutting line (A) and the second cutting line (B) is a preset distance (502).
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: May 6, 2025
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinliang Wang, Biqiang Huang, Jixiang Chen, Xin Fang
  • Publication number: 20250124843
    Abstract: A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 17, 2025
    Inventors: Xin FANG, Wenchao WANG, Sangjin PARK, Jixiang CHEN, Xiaolong CHEN, Lixia ZHANG
  • Patent number: 12271084
    Abstract: An array substrate, a method for manufacturing the array substrate and a display device. The array substrate includes: a base substrate including a display region and a peripheral region surrounding the display region; and a light-leakage protection film layer formed on the base substrate. The light-leakage protection film layer is arranged at the peripheral region and includes at least one first film layer, a light transmittance of each first film layer is smaller than or equal to a first threshold, and reflectivity of the first film layer is smaller than or equal to a second threshold.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 8, 2025
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinliang Wang, Jixiang Chen, Wenchao Wang, Sangjin Park
  • Publication number: 20250104663
    Abstract: A display substrate includes a base substrate, a first drive module, a second drive module, an array of sub-pixel circuits, rows of gate lines, and columns of data lines. A portion of sub-pixel circuits having the same color in the same row are electrically connected to one row of the gate line, another portion of sub-pixel circuits having the same color in the same row are electrically connected to another row of the gate line. The first drive module is electrically connected to a first end of the row of gate line and the second drive module is electrically connected to a second end of the another row of gate line. The first end and the second end are opposite ends. In the sub-pixel circuits located in the same row, at least two sub-pixel circuits at the same side of the data line are electrically connected to the data line.
    Type: Application
    Filed: February 23, 2023
    Publication date: March 27, 2025
    Inventors: Sangjin PARK, Jixiang CHEN, Wenchao WANG, Jinliang WANG, Xin FANG, Xu XU, Shanshan XU
  • Publication number: 20250022154
    Abstract: An initial display substrate comprising a product region and a to-be-processed region on periphery of the product region, the to-be-processed region comprising to-be-processed rounded corner regions at corners of the initial display substrate, each corner comprising major corner sides whose extension directions intersect, at least one to-be-processed rounded corner region comprising first positioning sub-region and two second positioning sub-regions, the major corner sides respectively defining edges of the second positioning sub-regions, the first positioning sub-region being between the second positioning sub-regions; first shielding blocks in the first positioning sub-region, each having arc shape protruding towards direction away from the product region, and the first shielding blocks being arranged in parallel at intervals; and second shielding blocks in each second positioning sub-region, a shape of the second shielding block is not exactly the same as that of the first shielding block.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 16, 2025
    Inventors: Xu XU, Biqiang HUANG, Shanshan XU, Wenchao WANG, Jixiang CHEN, Longgan HU
  • Patent number: 12131495
    Abstract: An initial display substrate comprising a product region and a to-be-processed region on periphery of the product region, the to-be-processed region comprising to-be-processed rounded corner regions at corners of the initial display substrate, each corner comprising major corner sides whose extension directions intersect, at least one to-be-processed rounded corner region comprising first positioning sub-region and two second positioning sub-regions, the major corner sides respectively defining edges of the second positioning sub-regions, the first positioning sub-region being between the second positioning sub-regions; first shielding blocks in the first positioning sub-region, each having arc shape protruding towards direction away from the product region, and the first shielding blocks being arranged in parallel at intervals; and second shielding blocks in each second positioning sub-region, the second shielding blocks being arranged in periodic pattern different from pattern of shielding blocks in a regio
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: October 29, 2024
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xu Xu, Biqiang Huang, Shanshan Xu, Wenchao Wang, Jixiang Chen, Longgan Hu
  • Publication number: 20240353722
    Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel comprises: a base substrate having multiple rows and multiple columns of sub-pixels; and a pixel electrode layer located on the base substrate, the pixel electrode layer comprising a plurality of pixel electrodes arranged apart from each other, and one sub-pixel comprising one pixel electrode, wherein the pixel electrode comprises: a first electrode strip and comb structures respectively connected to both sides of the first electrode strip, each comb structure consisting of a plurality of second electrode strips and a plurality of slits arranged alternately.
    Type: Application
    Filed: October 19, 2021
    Publication date: October 24, 2024
    Inventors: Baoqiang WANG, Xu XU, Wenchao WANG, Shanshan XU, Jinliang WANG, Xin FANG, Jixiang CHEN
  • Publication number: 20240280850
    Abstract: Provided are a display panel and a preparation method thereof and a display device. The display panel includes an array substrate, where the array substrate includes a first base, a first signal wire layer located on a side of the first base and an anti-reflection layer located between the first signal wire layer and the first base. The display panel further includes a display region and a non-display region; the first signal wire layer includes a first signal wire located in the display region, and the anti-reflection layer includes a first anti-reflection structure located in the display region and a second anti-reflection structure located in the non-display region. An orthographic projection of the first anti-reflection structure on a plane where the first base is located covers at least part of an orthographic projection of the first signal wire on the plane where the first base is located.
    Type: Application
    Filed: April 26, 2024
    Publication date: August 22, 2024
    Applicant: Xiamen Tianma Optoelectronics Co., Ltd.
    Inventors: Wenxing XI, Jixiang CHEN, Xuhui PENG, Qiaoning ZHENG, Hongyuan HUANG, Xiaolin WANG, Wei HUANG
  • Patent number: 11782320
    Abstract: The present disclosure provides a display substrate, a compensation method and a display substrate. The non-display area includes a first fan-out area and a second fan-out area arranged at two opposite sides of the display area along a first direction respectively. The display substrate further includes a plurality of data lines extending along the first direction, each data line includes a first portion, a second portion and a third portion, at least part of the first portion is arranged in the display area, the second portion is arranged in the first fan-out area, the third portion is arranged in the second fan-out area, and the data lines have a substantially same resistance.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: October 10, 2023
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Jixiang Chen, Wenchao Wang, Jinliang Wang, Shanshan Xu, Xu Xu, Xin Fang
  • Patent number: 11567358
    Abstract: Provided are a color film substrate and manufacturing method thereof, and a display panel and manufacturing method thereof. The color film substrate is divided into a display region, and a non-display region around a periphery of the display region and including an edge region at an edge of the color film substrate. The color film substrate includes base, color resist layer on the base and black matrix layer on the base at least in the display region. In the edge region, the color resist layer includes first sub color resist layer on the base and second sub color resist layer on the first sub color resist layer, the first sub color resist layer allows light in first wavelength range to transmit therethrough, the second sub color resist layer allows light in a second wavelength range to transmit therethrough, and the first wavelength range does not overlap the second wavelength range.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 31, 2023
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xin Fang, Jixiang Chen, Shanshan Xu, Longgan Hu, Wenchao Wang, Jinliang Wang, Sang Jin Park
  • Publication number: 20220308408
    Abstract: An array substrate, a method for manufacturing the array substrate and a display device. The array substrate includes: a base substrate including a display region and a peripheral region surrounding the display region; and a light-leakage protection film layer formed on the base substrate. The light-leakage protection film layer is arranged at the peripheral region and includes at least one first film layer, a light transmittance of each first film layer is smaller than or equal to a first threshold, and reflectivity of the first film layer is smaller than or equal to a second threshold.
    Type: Application
    Filed: September 30, 2020
    Publication date: September 29, 2022
    Applicants: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinliang WANG, Jixiang CHEN, Wenchao WANG, Sangjin PARK