Patents by Inventor Jixiang Hou

Jixiang Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230398072
    Abstract: A concentrate, characterized in that the concentrate contains a poorly soluble drug and a self-emulsifying carrier. The selfemulsifying carrier consists of the following substances: a composite emulsifier, which consists of phospholipid and nonphospholipid emulsifiers; an oil, which is medium chain triglyceride; and a co-emulsifier, which is anhydrous ethanol. The phospholipid is selected from soybean phospholipid, egg yolk lecithin, and a mixture thereof. The concentrate can be used to prepare an intravenous injection emulsion.
    Type: Application
    Filed: December 10, 2021
    Publication date: December 14, 2023
    Applicant: BEIJING DELIVERY PHARMACEUTICAL TECHNOLOGY CO., LTD
    Inventors: Cuishuan WU, Xiaobo CHENG, Dan ZHANG, Jixiang HOU, Boce ZHAO, Qiang ZHANG
  • Patent number: 9739833
    Abstract: A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N?1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N?1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jixiang Hou, Hailong Li, Li Min Liu, Yin Peng Lu, Liudi Wang
  • Publication number: 20160125957
    Abstract: A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N?1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N?1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode.
    Type: Application
    Filed: October 5, 2015
    Publication date: May 5, 2016
    Inventors: Jixiang Hou, Hailong Li, Li Min Liu, Yin Peng Lu, Liudi Wang