Patents by Inventor Jixing Chen
Jixing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240127880Abstract: A control circuit is provided, including a random module and an output module. A first input terminal of the random module receives a refresh count signal, a second input terminal receives random data, and a control terminal is connected to an output terminal of the output module. The random module processes the refresh count signal and the random data based on a row hammer refresh (RHR) signal output by the output module to obtain and output a random signal. A first input terminal of the output module receives the refresh count signal, a second input terminal is connected to an output terminal of the random module. The output module generates and outputs the RHR signal according to the random signal and the refresh count signal.Type: ApplicationFiled: August 16, 2023Publication date: April 18, 2024Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Lu LIU, Jixing CHEN
-
Publication number: 20240120431Abstract: Clean version of the Abstract A preparation method for growing a germanium sulfide (GeS2) single-crystal thin film on a SiO2 substrate includes: cleaning a surface of a substrate with acetone, ethanol and deionized water, where the substrate is a Si/SiO2 substrate or a SiO2 glass substrate; photoetching the substrate, spin-coating a photoresist, and performing photoetching and dry etching or wet etching to obtain a groove pattern; depositing a germanium (Ge)-crystal layer in the groove pattern of the substrate to obtain a treated substrate; and putting the treated substrate into a chemical vapor deposition (CVD) device for growth, a growth source being high-purity sulfur (S) powder and high-purity Ge powder, thereby obtaining a GeS2 single-crystal thin film on the SiO2 substrate. The preparation method can grow GeS2 single crystals on the SiO2 substrate. The GeS2 single crystals have a high crystalline quality and a small surface roughness.Type: ApplicationFiled: December 30, 2021Publication date: April 11, 2024Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGYInventors: Guoqiang LI, Sheng CHEN, Wenliang WANG, Jixing CHAI
-
Patent number: 11894042Abstract: A method for refreshing row hammer includes the following operations. A row hammer refresh instruction for a target word line is determined. According to the row hammer refresh instruction, a preset row hammer refresh signal is set to a valid state. The valid state of the preset row hammer refresh signal indicates that the row hammer refresh instruction is performed in a first refresh period. In response to detecting that the row hammer refresh instruction is not completed within the first refresh period, the valid state of the preset row hammer refresh signal will be continued to a next refresh period of the first refresh period.Type: GrantFiled: June 17, 2022Date of Patent: February 6, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jixing Chen
-
Publication number: 20240037230Abstract: A refresh control method includes: generating a first random number; and preforming, in response to execution times of a regular refresh operation reaching the first random number after execution of a previous row hammer refresh operation, a new row hammer refresh operation.Type: ApplicationFiled: August 17, 2023Publication date: February 1, 2024Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jixing CHEN, Lu LIU, Zhonglai LIU
-
Patent number: 11875045Abstract: A semiconductor memory and a method for density configuration of a bank of the semiconductor memory are provided. The method includes: determining a target bank to be configured of the semiconductor memory; determining a density configuration parameter of the target bank, the density configuration parameter being configured to represent a density to be configured for the target bank; determining a target code from a set of codes of the target bank based on the density configuration parameter of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure the density of the target bank.Type: GrantFiled: June 20, 2022Date of Patent: January 16, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jixing Chen, Weibing Shang
-
Patent number: 11869570Abstract: A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.Type: GrantFiled: February 11, 2022Date of Patent: January 9, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jixing Chen
-
Publication number: 20230420026Abstract: A refresh control circuit includes the following: an address output circuit configured to output a to-be-refreshed address signal including a block address signal and a row address signal; a block decoding circuit configured to: receive the block address signal; decode the block address signal and output a first block selection signal for selecting multiple data blocks from the memory array, in response to that the memory array is subjected to no row hammer attack, or decode the block address signal and output a second block selection signal for selecting one data block from the memory array, in response to that the memory array is subjected to a row hammer attack; and a row decoding circuit, configured to receive the row address signal, decode the row address signal and output a row selection signal.Type: ApplicationFiled: September 27, 2022Publication date: December 28, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Jixing CHEN, Liang CHEN
-
Patent number: 11848045Abstract: Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.Type: GrantFiled: August 7, 2021Date of Patent: December 19, 2023Assignee: Changxin Memory Technologies, Inc.Inventors: Weibing Shang, Jixing Chen, Xianjun Wu
-
Publication number: 20230282265Abstract: A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.Type: ApplicationFiled: September 30, 2022Publication date: September 7, 2023Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jixing CHEN
-
Patent number: 11721383Abstract: A refresh circuit includes: a signal generation module, configured to generate an inversion signal and a carry signal based on a refresh command; an adjustment unit, configured to generate, if a first refresh signal and a second refresh signal are generated based on the refresh command, an inversion adjustment signal according to the inversion signal, and generate, if only the first refresh signal is generated based on the refresh command, the inversion adjustment signal according to an inversion signal corresponding to a first refresh signal generated based on a current refresh command, and generate the inversion adjustment signal only according to an inversion signal corresponding to a second refresh signal generated based on a next refresh command; and a counting module, configured to generate a first output signal and a second output signal, and invert the first output signal based on the inversion adjustment signal.Type: GrantFiled: April 7, 2022Date of Patent: August 8, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jixing Chen
-
Publication number: 20230178135Abstract: An address refresh circuit and method, a memory, and an electronic device are provided. The address refresh circuit includes a selection circuit and a decoding circuit. The selection circuit is configured to acquire a strobe signal, a redundancy address signal and a normal address signal, and select, within each of a first pulse duration and a second pulse duration and based on the strobe signal, one of the redundancy address signal or the normal address signal as a target address signal; the first pulse duration and the second pulse duration belong to the same refresh cycle, and the second pulse duration is later than the first pulse duration. The decoding circuit is configured to decode the target address signal to obtain and output a decoded signal.Type: ApplicationFiled: July 1, 2022Publication date: June 8, 2023Inventors: Jixing CHEN, Enpeng GAO
-
Publication number: 20230120815Abstract: A refresh circuit includes: a signal generation module, configured to generate an inversion signal and a carry signal based on a refresh command; an adjustment unit, configured to generate, if a first refresh signal and a second refresh signal are generated based on the refresh command, an inversion adjustment signal according to the inversion signal, and generate, if only the first refresh signal is generated based on the refresh command, the inversion adjustment signal according to an inversion signal corresponding to a first refresh signal generated based on a current refresh command, and generate the inversion adjustment signal only according to an inversion signal corresponding to a second refresh signal generated based on a next refresh command; and a counting module, configured to generate a first output signal and a second output signal, and invert the first output signal based on the inversion adjustment signal.Type: ApplicationFiled: April 7, 2022Publication date: April 20, 2023Inventor: Jixing CHEN
-
Publication number: 20230039810Abstract: A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.Type: ApplicationFiled: February 11, 2022Publication date: February 9, 2023Inventor: Jixing Chen
-
Publication number: 20230012916Abstract: A semiconductor memory and a method for density configuration of a bank of the semiconductor memory are provided. The method includes: determining a target bank to be configured of the semiconductor memory; determining a density configuration parameter of the target bank, the density configuration parameter being configured to represent a density to be configured for the target bank; determining a target code from a set of codes of the target bank based on the density configuration parameter of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure the density of the target bank.Type: ApplicationFiled: June 20, 2022Publication date: January 19, 2023Inventors: Jixing CHEN, Weibing Shang
-
Publication number: 20210398586Abstract: Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.Type: ApplicationFiled: August 7, 2021Publication date: December 23, 2021Inventors: Weibing SHANG, Jixing CHEN, Xianjun WU
-
Patent number: 9570700Abstract: Disclosed are an organic electroluminescent device and a preparation method thereof. The organic electroluminescent device is a top-emitting organic electroluminescent device having a reversed structure, and the preparation method is: dissolving zinc oxide with acetic acid to obtain a zinc oxide solution with a concentration of 0.3 g/ml-0.6 g/ml, adding a phthalocyanine substance in a mass of 1%-10% of the mass of the zinc oxide to obtain a mixture, spin-coating the mixture on a glass substrate (1) and then drying to obtain a cathode (2), and then preparing by vapor deposition, an electron injection layer (3), an electron transport layer (4), a luminescent layer (5), a hole transport layer (6), a hole injection layer (7) and an anode (8), successively, so as to obtain the organic electroluminescent device.Type: GrantFiled: September 28, 2012Date of Patent: February 14, 2017Assignees: OCEAN'S KING LIGHTING SCIENCE & TECHNOLOGY CO., LTD., SHENZHEN OCEAN'S KING LIGHTING ENGINEERING CO., LTD.Inventors: Mingjie Zhou, Ping Wang, Hui Huang, Jixing Chen
-
Patent number: 9270084Abstract: Cerium doped magnesium barium tungstate luminescent thin film, manufacturing method and application thereof are provided, said method for manufacturing cerium doped magnesium barium tungstate luminescent thin film comprises the following steps: mixing MgO, BaO, WO3 and Ce2O3, sintering for forming sputtering target, forming the precursor of cerium doped magnesium barium tungstate luminescent thin film by magnetron sputtering, annealing the precursor of cerium doped magnesium barium tungstate luminescent thin film, and then forming cerium doped magnesium barium tungstate luminescent thin film. Said cerium doped magnesium barium tungstate luminescent thin film exhibits high luminescence efficiency and high light emitting peaks in red and blue regions. Said method presents the advantages of simplified operation, less cost, and suitable for industrial preparation.Type: GrantFiled: June 28, 2011Date of Patent: February 23, 2016Assignee: Ocean's King Lighting Science & Technology Co., Ltd.Inventors: Mingjie Zhou, Ping Wang, Jixing Chen, Hui Huang
-
Publication number: 20150263285Abstract: Disclosed are a polymer solar cell and a preparation method thereof. The preparation method comprises: successively preparing on a clean glass substrate (1), a cathode (2), an electronic buffer layer (3) and an active layer (4) by the steps of dissolving poly(3,4-ethylenedioxythiophene) and polymerized p-styrene sulphonic acid, dissolving zinc oxide into acetic acid to obtain a zinc oxide solution, mixing the zinc oxide solution with the solution of poly(3,4-ethylenedioxythiophene) and polymerized p-styrene sulphonic acid to obtain a mixed solution, spin-coating the mixed solution on the active layer (4) and then by drying to obtain the anode (5), and finally obtain the polymer solar cell.Type: ApplicationFiled: September 28, 2012Publication date: September 17, 2015Applicant: OCEAN'S KING LIGHTING SCIENCE & TECHNOLOGY CO., LTD.Inventors: Mingjie ZHOU, Ping WANG, Hui HUANG, Jixing CHEN
-
Publication number: 20150255745Abstract: Disclosed are an organic electroluminescent device and a preparation method thereof. The organic electroluminescent device is a top-emitting organic electroluminescent device having a reversed structure, and the preparation method is: dissolving zinc oxide with acetic acid to obtain a zinc oxide solution with a concentration of 0.3 g/ml-0.6 g/ml, adding a phthalocyanine substance in a mass of 1%-10% of the mass of the zinc oxide to obtain a mixture, spin-coating the mixture on a glass substrate (1) and then drying to obtain a cathode (2), and then preparing by vapor deposition, an electron injection layer (3), an electron transport layer (4), a luminescent layer (5), a hole transport layer (6), a hole injection layer (7) and an anode (8), successively, so as to obtain the organic electroluminescent device.Type: ApplicationFiled: September 28, 2012Publication date: September 10, 2015Applicant: OCEAN'S KING LIGHTING SCIENCE & TECHNOLOGY CO., LTDInventors: Mingjie Zhou, Ping Wang, Hui Huang, Jixing Chen
-
Publication number: 20140332796Abstract: An organic electroluminescence device (100, 200) comprises a substrate (110), an anode (130), a light emitting layer (160) and a cathode (190) stacked sequentially. The anode (130) comprises a light transmittance increased layer (131), a conductive layer (132) and a hole injection auxiliary layer (133) stacked on the substrate (110) sequentially. The materials of the light transmittance increased layer (131) are inorganic compounds of zinc with a light transmittance of 400 nm to 800 nm in the visible region and a refractive index greater than 2.3. The material of the conductive layer (132) is graphene. The utilization of light transmittance increased principle for multilayer anode structure can make the light transmittance of the anode in the visible region high and surface resistance low.Type: ApplicationFiled: March 31, 2012Publication date: November 13, 2014Inventors: Mingjie Zhou, Ping Wang, Xiaoming Feng, Jixing Chen